From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by sourceware.org (Postfix) with ESMTPS id 1118C3858D20 for ; Tue, 8 Aug 2023 21:02:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1118C3858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-686ea67195dso4521732b3a.2 for ; Tue, 08 Aug 2023 14:02:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1691528577; x=1692133377; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=2vRlWsGzHhN34YjrzZjth2ABHorOHBNqkCzx/hEy110=; b=jVFyv5EfXsqRH8/IhJQ1p2UnYVxpAmCq+V110caxuQB4SrV/Cnx/oArNjEcnrbyeuU DtuZsHHlmAcCDp2PaRngkMVr3iCEZsM6F/qMZRYYv8gQvBZphUHAYeTIpgRANhQIVztq dbtXMWZo6v5r2Z0Ufb2cJa2JXShl9t+xZiJnj01QE9AgxhfXyxODrPsmQAWeEK8WD/4r S+aeJtvhJipHHoYl8jsT1/SeCarVjGNzPLY2T9V5VXJ1gNI6oabSjiS1OkzYnzxSVDfr 1QXgu5I8Gnv2A58B6D7FZve6PoKbs/FFK4W/n1ngiWYNhEjJLbmcqdfiTfTiM3GYVDMi hd/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691528577; x=1692133377; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=2vRlWsGzHhN34YjrzZjth2ABHorOHBNqkCzx/hEy110=; b=CkqyXwYGT//LneQZpMSKzbW1331rav/H8fAn8I50MThFloNBMzbnp9Q186mZ3G96mJ islc7Sisc+L+q/tyXJBkxzIpu7tGuHsMlEX4rCe2CsQvUg/79JOC1I32iLB27qnIHx+q VihdOI79G6vV72cOIix42x+oslvgAjr8EJbW8yPzsGdhc9JeghPvzTDi/cMhutdQ4+SF oqe3Fki7xrxCCBX52vxccJvbYpZIpWm7r1iWTIne4Hrg98wfDfjKj8HK2M0ICty5Ay+U Xu0m16fGlLWvIJ2ufEKu5bDbiMe5SnjHC5NEnXYNLtIWU01yzgV6uM4qNhHvptxuuStS Hn4g== X-Gm-Message-State: AOJu0Yw5F5wARn3XRupmHAGLRGN39+RCnwXOndSrIXx+8CTXAKaNTLVb vhzv2/m+sXWLnJbllJCy45OTow== X-Google-Smtp-Source: AGHT+IHm4i/OD6DaaeLgRvtOlgPLhoCq19QKkfkYISZK0WNMwPSOua6BQzUHGm/T0vdnq8JyeHj+Zw== X-Received: by 2002:a05:6a00:2293:b0:687:189c:4e26 with SMTP id f19-20020a056a00229300b00687189c4e26mr770617pfe.2.1691528577382; Tue, 08 Aug 2023 14:02:57 -0700 (PDT) Received: from [10.0.16.165] ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id u16-20020aa78490000000b00682936d04ccsm8466463pfn.180.2023.08.08.14.02.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 08 Aug 2023 14:02:57 -0700 (PDT) Message-ID: Date: Tue, 8 Aug 2023 14:02:56 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH V2] riscv: generate builtin macro for compilation with strict alignment: Content-Language: en-US To: Edwin Lu , gcc-patches@gcc.gnu.org Cc: gnu-toolchain@rivosinc.com References: <20230808202458.3094615-1-ewlu@rivosinc.com> From: Vineet Gupta In-Reply-To: <20230808202458.3094615-1-ewlu@rivosinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_SHORT,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 8/8/23 13:24, Edwin Lu wrote: > diff --git a/gcc/testsuite/gcc.target/riscv/attribute-1.c b/gcc/testsuite/gcc.target/riscv/attribute-1.c > index bc919c586b6..4b077c980a4 100644 > --- a/gcc/testsuite/gcc.target/riscv/attribute-1.c > +++ b/gcc/testsuite/gcc.target/riscv/attribute-1.c > @@ -2,5 +2,20 @@ > /* { dg-options "-mriscv-attribute" } */ > int foo() > { > + Maybe add a comment that in absence of -m[no-]strict-align, we use the cpu tune param -> slow_unaligned_access and that default mcpu is rocket which has that set to _slow. > +#if defined(__riscv_unaligned_avoid) > +#error "__riscv_unaligned_avoid is unexpectedly set" > +#endif Lets first check what is really expected. #if !defined (_slow) #error > + > +/* Check __riscv_unaligned_slow xor __riscv_unaligned_fast is set. */ > +#if !defined(__riscv_unaligned_slow) && !defined(__riscv_unaligned_fast) > +#error "either __riscv_unaligned_slow or__riscv_unaligned_fast is not set" > +#endif > + > +#if defined(__riscv_unaligned_slow) && defined(__riscv_unaligned_fast) > +#error "both __riscv_unaligned_slow and__riscv_unaligned_fast are set" > +#endif > + I think we can simplify this a bit (sorry I if wasn't clear enough in our off-list discussions). We now need to ensure that unexpected toggles are NOT defined: #if defined(_avoid) || defined(_fast) #error I don't think we need to check for the combinations as that is covered by first one and this. While separate #error prints for 2 failures are ideal, personally it feels excessive given that the current implementation will only ever generate 1 of them. If a future code change breaks that assumption, the onus is on that change to fix/update the errors. > +return 0; > } > /* { dg-final { scan-assembler ".attribute arch" } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/attribute-4.c b/gcc/testsuite/gcc.target/riscv/attribute-4.c > index 7c565c4963e..c505dbae2aa 100644 > --- a/gcc/testsuite/gcc.target/riscv/attribute-4.c > +++ b/gcc/testsuite/gcc.target/riscv/attribute-4.c > @@ -2,5 +2,19 @@ > /* { dg-options "-mriscv-attribute -mstrict-align" } */ > int foo() > { > + > +#if !defined(__riscv_unaligned_avoid) > +#error "__riscv_unaligned_avoid is not set" > +#endif > + > +#if defined(__riscv_unaligned_fast) > +#error "__riscv_unaligned_fast is unexpectedly set" > +#endif > + > +#if defined(__riscv_unaligned_slow) > +#error "__riscv_unaligned_slow is unexpectedly set" > +#endif > + > + return 0; > } > /* { dg-final { scan-assembler ".attribute unaligned_access, 0" } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/attribute-5.c b/gcc/testsuite/gcc.target/riscv/attribute-5.c > index ee9cf693be6..45afa6c464d 100644 > --- a/gcc/testsuite/gcc.target/riscv/attribute-5.c > +++ b/gcc/testsuite/gcc.target/riscv/attribute-5.c > @@ -2,5 +2,20 @@ > /* { dg-options "-mriscv-attribute -mno-strict-align" } */ > int foo() > { > + > +#if defined(__riscv_unaligned_avoid) > +#error "__riscv_unaligned_avoid is unexpectedly set" > +#endif > + > +/* Check __riscv_unaligned_slow xor __riscv_unaligned_fast is set. */ > +#if !defined(__riscv_unaligned_slow) && !defined(__riscv_unaligned_fast) > +#error "either __riscv_unaligned_slow or__riscv_unaligned_fast is not set" > +#endif > + > +#if defined(__riscv_unaligned_slow) && defined(__riscv_unaligned_fast) > +#error "both __riscv_unaligned_slow and__riscv_unaligned_fast are set" > +#endif Same as my comment for attribute-1. Please recheck all of them. > + > +return 0; > } > /* { dg-final { scan-assembler ".attribute unaligned_access, 1" } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-1.c b/gcc/testsuite/gcc.target/riscv/predef-align-1.c > new file mode 100644 > index 00000000000..2a889dd9284 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/predef-align-1.c > @@ -0,0 +1,20 @@ > +/* { dg-do compile } */ > +/* { dg-options "-mtune=thead-c906" } */ > + > +int main() { > + > +/* thead-c906 default is cpu tune param unaligned access fast */ > +#if !defined(__riscv_unaligned_fast) > +#error "__riscv_unaligned_fast is not set" > +#endif > + > +#if defined(__riscv_unaligned_slow) > +#error "__riscv_unaligned_slow is unexpectedly set" > +#endif > + > +#if defined(__risvc_unaligned_avoid) > +#error "__riscv_unaligned_avoid is unexpectedly set" > +#endif > + > + return 0; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-2.c b/gcc/testsuite/gcc.target/riscv/predef-align-2.c > new file mode 100644 > index 00000000000..76cbce60d9f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/predef-align-2.c > @@ -0,0 +1,19 @@ > +/* { dg-do compile } */ > +/* { dg-options "-mtune=thead-c906 -mstrict-align" } */ > + > +int main() { > + > +#if !defined(__riscv_unaligned_avoid) > +#error "__riscv_unaligned_avoid is not set" > +#endif > + > +#if defined(__riscv_unaligned_fast) > +#error "__riscv_unaligned_fast is unexpectedly set" > +#endif > + > +#if defined(__riscv_unaligned_slow) > +#error "__riscv_unaligned_slow is unexpectedly set" > +#endif > + > + return 0; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-3.c b/gcc/testsuite/gcc.target/riscv/predef-align-3.c > new file mode 100644 > index 00000000000..f8caef48180 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/predef-align-3.c > @@ -0,0 +1,20 @@ > +/* { dg-do compile } */ > +/* { dg-options "-mtune=thead-c906 -mno-strict-align" } */ > + > +int main() { > + > +/* thead-c906 default is cpu tune param unaligned access fast */ > +#if !defined(__riscv_unaligned_fast) > +#error "__riscv_unaligned_fast is not set" > +#endif > + > +#if defined(__riscv_unaligned_slow) > +#error "__riscv_unaligned_slow is unexpectedly set" > +#endif > + > +#if defined(__risvc_unaligned_avoid) > +#error "__riscv_unaligned_avoid is unexpectedly set" > +#endif > + > + return 0; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-4.c b/gcc/testsuite/gcc.target/riscv/predef-align-4.c > new file mode 100644 > index 00000000000..ac0400a1383 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/predef-align-4.c > @@ -0,0 +1,20 @@ > +/* { dg-do compile } */ > +/* { dg-options "-mtune=rocket" } */ > + > +int main() { > + > +/* rocket default is cpu tune param unaligned access slow */ > +#if !defined(__riscv_unaligned_slow) > +#error "__riscv_unaligned_slow is not set" > +#endif > + > +#if defined(__riscv_unaligned_fast) > +#error "__riscv_unaligned_fast is unexpectedly set" > +#endif > + > +#if defined(__risvc_unaligned_avoid) > +#error "__riscv_unaligned_avoid is unexpectedly set" > +#endif > + > + return 0; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-5.c b/gcc/testsuite/gcc.target/riscv/predef-align-5.c > new file mode 100644 > index 00000000000..26f8ce793c0 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/predef-align-5.c > @@ -0,0 +1,19 @@ > +/* { dg-do compile } */ > +/* { dg-options "-mtune=rocket -mstrict-align" } */ > + > +int main() { > + > +#if !defined(__riscv_unaligned_avoid) > +#error "__riscv_unaligned_avoid is not set" > +#endif > + > +#if defined(__riscv_unaligned_fast) > +#error "__riscv_unaligned_fast is unexpectedly set" > +#endif > + > +#if defined(__riscv_unaligned_slow) > +#error "__riscv_unaligned_slow is unexpectedly set" > +#endif > + > + return 0; > +} > diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-6.c b/gcc/testsuite/gcc.target/riscv/predef-align-6.c > new file mode 100644 > index 00000000000..241d893a677 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/predef-align-6.c > @@ -0,0 +1,20 @@ > +/* { dg-do compile } */ > +/* { dg-options "-mtune=rocket -mno-strict-align" } */ > + > +int main() { > + > +/* rocket default is cpu tune param unaligned access slow */ > +#if !defined(__riscv_unaligned_slow) > +#error "__riscv_unaligned_slow is not set" > +#endif > + > +#if defined(__riscv_unaligned_fast) > +#error "__riscv_unaligned_fast is unexpectedly set" > +#endif > + > +#if defined(__risvc_unaligned_avoid) > +#error "__riscv_unaligned_avoid is unexpectedly set" > +#endif > + > + return 0; > +}