From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id DA0023858CDA; Wed, 26 Apr 2023 09:35:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DA0023858CDA Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com Received: from pps.filterd (m0353722.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33Q9WeMq032043; Wed, 26 Apr 2023 09:35:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=message-id : date : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding : mime-version; s=pp1; bh=qUEuscRopI40G8o630QbiVAvHNpq9NCUtzcklDA75M8=; b=KJEHKzwRjFNACwQa78tK4syRThMxRARITQwIQ0yTds9YvjzGixOznrxWpXQjXwDEiJpB Mg2t45Bw/kDWKPwjtFhLwORPJv3c+7gOmPy5Imqfp4gKsmrnxsOEWfrdOLiZVvIGpu3n OKtJvwABZgK4yHII9Azjz6UjKUEBeFdZW6XlJVjLhF/S7QOptuAltGRGqnaNej+elKJJ 0ifPYNUlo9VG+g2cjNRox9jLqbJrVn4/Gm17CFny+J4FWv3/jJm5d6cC5lkVBp7PGP8F DYHoXb5gwp/s/BdJ5/dKwCCZCYUgHqHxWZZkdFByGPbHxvH5W0If+1Ktz0XH6qgwqeni 7A== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3q71dq05n7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); 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Wed, 26 Apr 2023 09:35:26 GMT Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 11B4A20043; Wed, 26 Apr 2023 09:35:26 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C53D520040; Wed, 26 Apr 2023 09:35:23 +0000 (GMT) Received: from [9.177.90.69] (unknown [9.177.90.69]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 26 Apr 2023 09:35:23 +0000 (GMT) Message-ID: Date: Wed, 26 Apr 2023 17:35:21 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCH V3] rs6000: Load high and low part of 64bit constant independently Content-Language: en-US To: Jiufu Guo Cc: segher@kernel.crashing.org, dje.gcc@gmail.com, linkw@gcc.gnu.org, gcc-patches@gcc.gnu.org References: <20230104065140.91578-1-guojiufu@linux.ibm.com> From: "Kewen.Lin" In-Reply-To: <20230104065140.91578-1-guojiufu@linux.ibm.com> Content-Type: text/plain; charset=UTF-8 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: FmpfpP-TWbaM1V5Oxu3Raih9z33XapP2 X-Proofpoint-ORIG-GUID: ZimUBptaEjgoaxu5G8i6Au-znRKdAJYa Content-Transfer-Encoding: 7bit X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-26_04,2023-04-26_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 spamscore=0 adultscore=0 mlxlogscore=999 impostorscore=0 mlxscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304260086 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,NICE_REPLY_A,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Jeff, on 2023/1/4 14:51, Jiufu Guo wrote: > Hi, > > Compare with previous version, this patch updates the comments only. > https://gcc.gnu.org/pipermail/gcc-patches/2022-December/608293.html > > For a complicate 64bit constant, below is one instruction-sequence to > build: > lis 9,0x800a > ori 9,9,0xabcd > sldi 9,9,32 > oris 9,9,0xc167 > ori 9,9,0xfa16 > > while we can also use below sequence to build: > lis 9,0xc167 > lis 10,0x800a > ori 9,9,0xfa16 > ori 10,10,0xabcd > rldimi 9,10,32,0 > This sequence is using 2 registers to build high and low part firstly, > and then merge them. > > In parallel aspect, this sequence would be faster. (Ofcause, using 1 more > register with potential register pressure). > > The instruction sequence with two registers for parallel version can be > generated only if can_create_pseudo_p. Otherwise, the one register > sequence is generated. > > Bootstrap and regtest pass on ppc64{,le}. > Is this ok for trunk? OK for trunk, thanks for the improvement! BR, Kewen > > > BR, > Jeff(Jiufu) > > > gcc/ChangeLog: > > * config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Generate > more parallel code if can_create_pseudo_p. > > gcc/testsuite/ChangeLog: > > * gcc.target/powerpc/parall_5insn_const.c: New test. > > --- > gcc/config/rs6000/rs6000.cc | 39 +++++++++++++------ > .../gcc.target/powerpc/parall_5insn_const.c | 27 +++++++++++++ > 2 files changed, 54 insertions(+), 12 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c > > diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc > index 6ac3adcec6b..b4f03499252 100644 > --- a/gcc/config/rs6000/rs6000.cc > +++ b/gcc/config/rs6000/rs6000.cc > @@ -10366,19 +10366,34 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c) > } > else > { > - temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode); > - > - emit_move_insn (temp, GEN_INT (sext_hwi (ud4 << 16, 32))); > - if (ud3 != 0) > - emit_move_insn (temp, gen_rtx_IOR (DImode, temp, GEN_INT (ud3))); > + if (can_create_pseudo_p ()) > + { > + /* lis HIGH,UD4 ; ori HIGH,UD3 ; > + lis LOW,UD2 ; ori LOW,UD1 ; rldimi LOW,HIGH,32,0. */ > + rtx high = gen_reg_rtx (DImode); > + rtx low = gen_reg_rtx (DImode); > + HOST_WIDE_INT num = (ud2 << 16) | ud1; > + rs6000_emit_set_long_const (low, sext_hwi (num, 32)); > + num = (ud4 << 16) | ud3; > + rs6000_emit_set_long_const (high, sext_hwi (num, 32)); > + emit_insn (gen_rotldi3_insert_3 (dest, high, GEN_INT (32), low, > + GEN_INT (0xffffffff))); > + } > + else > + { > + /* lis DEST,UD4 ; ori DEST,UD3 ; rotl DEST,32 ; > + oris DEST,UD2 ; ori DEST,UD1. */ > + emit_move_insn (dest, GEN_INT (sext_hwi (ud4 << 16, 32))); > + if (ud3 != 0) > + emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3))); > > - emit_move_insn (ud2 != 0 || ud1 != 0 ? temp : dest, > - gen_rtx_ASHIFT (DImode, temp, GEN_INT (32))); > - if (ud2 != 0) > - emit_move_insn (ud1 != 0 ? temp : dest, > - gen_rtx_IOR (DImode, temp, GEN_INT (ud2 << 16))); > - if (ud1 != 0) > - emit_move_insn (dest, gen_rtx_IOR (DImode, temp, GEN_INT (ud1))); > + emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32))); > + if (ud2 != 0) > + emit_move_insn (dest, > + gen_rtx_IOR (DImode, dest, GEN_INT (ud2 << 16))); > + if (ud1 != 0) > + emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1))); > + } > } > } > > diff --git a/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c b/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c > new file mode 100644 > index 00000000000..e3a9a7264cf > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c > @@ -0,0 +1,27 @@ > +/* { dg-do run } */ > +/* { dg-options "-O2 -mno-prefixed -save-temps" } */ > +/* { dg-require-effective-target has_arch_ppc64 } */ > + > +/* { dg-final { scan-assembler-times {\mlis\M} 4 } } */ > +/* { dg-final { scan-assembler-times {\mori\M} 4 } } */ > +/* { dg-final { scan-assembler-times {\mrldimi\M} 2 } } */ > + > +void __attribute__ ((noinline)) foo (unsigned long long *a) > +{ > + /* 2 lis + 2 ori + 1 rldimi for each constant. */ > + *a++ = 0x800aabcdc167fa16ULL; > + *a++ = 0x7543a876867f616ULL; > +} > + > +long long A[] = {0x800aabcdc167fa16ULL, 0x7543a876867f616ULL}; > +int > +main () > +{ > + long long res[2]; > + > + foo (res); > + if (__builtin_memcmp (res, A, sizeof (res)) != 0) > + __builtin_abort (); > + > + return 0; > +}