From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 94654 invoked by alias); 17 Jul 2018 13:33:38 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 94222 invoked by uid 89); 17 Jul 2018 13:33:38 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-6.9 required=5.0 tests=BAYES_00,GIT_PATCH_3,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 17 Jul 2018 13:33:36 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 29D3E18A; Tue, 17 Jul 2018 06:33:35 -0700 (PDT) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.206.23]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C305E3F5B1; Tue, 17 Jul 2018 06:33:33 -0700 (PDT) Subject: Re: [GCC][PATCH][Aarch64] Exploiting BFXIL when OR-ing two AND-operations with appropriate bitmasks To: Richard Henderson , Sam Tebbs , Sudakshina Das , "gcc-patches@gcc.gnu.org" Cc: nd , marcus.shawcroft@arm.com, james.greenhalgh@arm.com References: <14ec9e29-9ec0-cd70-8a2c-c00723e96427@arm.com> <3e07b208-6de4-1af2-2e6f-72f330239bbd@arm.com> <1487cf4e-b5d4-3ff2-ddd2-90482a607666@twiddle.net> From: "Richard Earnshaw (lists)" Openpgp: preference=signencrypt Message-ID: Date: Tue, 17 Jul 2018 13:33:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 In-Reply-To: <1487cf4e-b5d4-3ff2-ddd2-90482a607666@twiddle.net> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-SW-Source: 2018-07/txt/msg00926.txt.bz2 On 17/07/18 02:33, Richard Henderson wrote: > On 07/16/2018 10:10 AM, Sam Tebbs wrote: >> +++ b/gcc/config/aarch64/aarch64.c >> @@ -1439,6 +1439,14 @@ aarch64_hard_regno_caller_save_mode (unsigned regno, unsigned, >> return SImode; >> } >> >> +/* Implement IS_LEFT_CONSECUTIVE. Check if an integer's bits are consecutive >> + ones from the MSB. */ >> +bool >> +aarch64_is_left_consecutive (HOST_WIDE_INT i) >> +{ >> + return (i | (i - 1)) == HOST_WIDE_INT_M1; >> +} >> + > ... >> +(define_insn "*aarch64_bfxil" >> + [(set (match_operand:DI 0 "register_operand" "=r") >> + (ior:DI (and:DI (match_operand:DI 1 "register_operand" "r") >> + (match_operand 3 "const_int_operand")) >> + (and:DI (match_operand:DI 2 "register_operand" "0") >> + (match_operand 4 "const_int_operand"))))] >> + "INTVAL (operands[3]) == ~INTVAL (operands[4]) >> + && aarch64_is_left_consecutive (INTVAL (operands[4]))" > > Better is to use a define_predicate to merge both that second test and the > const_int_operand. > > (I'm not sure about the "left_consecutive" language either. > Isn't it more descriptive to say that op3 is a power of 2 minus 1?) > > (define_predicate "pow2m1_operand" > (and (match_code "const_int") > (match_test "exact_pow2 (INTVAL(op) + 1) > 0"))) ITYM exact_log2() R. > > and use > > (match_operand:DI 3 "pow2m1_operand") > > and then just the > > INTVAL (operands[3]) == ~INTVAL (operands[4]) > > test. > > Also, don't omit the modes for the constants. > Also, there's no reason this applies only to DI mode; > use the GPI iterator and % in the output template. > >> + HOST_WIDE_INT op3 = INTVAL (operands[3]); >> + operands[3] = GEN_INT (ceil_log2 (op3)); >> + output_asm_insn ("bfxil\\t%0, %1, 0, %3", operands); >> + return ""; > > You can just return the string that you passed to output_asm_insn. > >> + } >> + [(set_attr "type" "bfx")] > > The other aliases of the BFM insn use type "bfm"; > "bfx" appears to be aliases of UBFM and SBFM. > Not that it appears to matter to the scheduling > descriptions, but it is inconsistent. > > > r~ >