From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 126975 invoked by alias); 5 Aug 2019 03:41:55 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 126967 invoked by uid 89); 5 Aug 2019 03:41:55 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-18.1 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,MIME_CHARSET_FARAWAY,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.1 spammy=rotatert, sk:VECTOR_, sud, dgfinal X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 05 Aug 2019 03:41:53 +0000 Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x753fhhl128815 for ; Sun, 4 Aug 2019 23:41:52 -0400 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 2u67x3h1kd-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sun, 04 Aug 2019 23:41:51 -0400 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Mon, 5 Aug 2019 04:41:46 +0100 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x753fjmI49479822 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 5 Aug 2019 03:41:45 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9D26B42047; Mon, 5 Aug 2019 03:41:45 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3BE0B42041; Mon, 5 Aug 2019 03:41:43 +0000 (GMT) Received: from kewenlins-mbp.cn.ibm.com (unknown [9.200.147.87]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 5 Aug 2019 03:41:42 +0000 (GMT) Subject: Re: [PATCH V5, rs6000] Support vrotr3 for int vector types To: Segher Boessenkool Cc: GCC Patches , Jakub Jelinek , Richard Biener , richard.sandiford@arm.com, Bill Schmidt References: <20190717134025.GJ20882@gate.crashing.org> <83f8448e-3c59-8991-2176-729d87e08a86@linux.ibm.com> <20190718194818.GT20882@gate.crashing.org> <20190719150647.GZ20882@gate.crashing.org> <20190725134958.GR20882@gate.crashing.org> <20190726141004.GA31406@gate.crashing.org> <85937573-94ae-8a13-2cf6-5d4b9edf97e2@linux.ibm.com> <20190803205221.GE31406@gate.crashing.org> From: "Kewen.Lin" Date: Mon, 05 Aug 2019 03:41:00 -0000 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.14; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20190803205221.GE31406@gate.crashing.org> Content-Type: multipart/mixed; boundary="------------02F797A7C2E35F36F0E60D38" x-cbid: 19080503-0008-0000-0000-0000030540A5 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19080503-0009-0000-0000-0000A17F445C Message-Id: X-IsSubscribed: yes X-SW-Source: 2019-08/txt/msg00225.txt.bz2 This is a multi-part message in MIME format. --------------02F797A7C2E35F36F0E60D38 Content-Type: text/plain; charset=gbk Content-Transfer-Encoding: 8bit Content-length: 2143 Hi Segher, on 2019/8/4 ÉÏÎç4:52, Segher Boessenkool wrote: > Hi! > > I somehow lost track of this email, sorry. > > On Fri, Aug 02, 2019 at 04:59:44PM +0800, Kewen.Lin wrote: >> As to the predicate name and usage, I checked the current vector shifts, >> they don't need to check const_vector specially (like right to left >> conversion), excepting for the one "vec_shr_", but it checks for >> scalar const int. > > I don't understand why we want to expand rotate-by-vector-of-immediates > if we have no insns for that? If you just use vint_operand, what happens > then? > You are right, if we just use vint_operand, the functionality should be the same, the only small difference is the adjusted constant rotation number isn't masked, but it would be fine for functionality. One example for ULL >r 8, with const vector handling, it gets xxspltib 33,56 Without the handling, it gets xxsplitb 33,248 But I agree that it's trivial and unified it as below attached patch. >> +/* { dg-options "-O3" } */ >> +/* { dg-require-effective-target powerpc_altivec_ok } */ > > If you use altivec_ok, you need to use -maltivec in the options, too. > This test should probably work with -O2 as well; use that, if possible. > Sorry, the test case depends on vectorization which isn't enabled at -O2 by default. >> +/* { dg-require-effective-target powerpc_p8vector_ok } */ > > I don't think we need this anymore? Not sure. > I thought -mdejagnu-cpu=power8 can only ensure power8 cpu setting takes preference, but can't guarantee the current driver supports power8 complication. As your comments, I guess since gcc configuration don't have without-cpu= etc., the power8 support should be always guaranteed? Thanks, Kewen ----------------- gcc/ChangeLog 2019-08-05 Kewen Lin * config/rs6000/vector.md (vrotr3): New define_expand. gcc/testsuite/ChangeLog 2019-08-05 Kewen Lin * gcc.target/powerpc/vec_rotate-1.c: New test. * gcc.target/powerpc/vec_rotate-2.c: New test. * gcc.target/powerpc/vec_rotate-3.c: New test. * gcc.target/powerpc/vec_rotate-4.c: New test. --------------02F797A7C2E35F36F0E60D38 Content-Type: text/plain; charset=UTF-8; x-mac-type="0"; x-mac-creator="0"; name="expand_v6.diff" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="expand_v6.diff" Content-length: 5092 diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 70bcfe02e22..886cbad1655 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -1260,6 +1260,19 @@ "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" "") +;; Expanders for rotatert to make use of vrotl +(define_expand "vrotr3" + [(set (match_operand:VEC_I 0 "vint_operand") + (rotatert:VEC_I (match_operand:VEC_I 1 "vint_operand") + (match_operand:VEC_I 2 "vint_operand")))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" +{ + rtx rot_count = gen_reg_rtx (mode); + emit_insn (gen_neg2 (rot_count, operands[2])); + emit_insn (gen_vrotl3 (operands[0], operands[1], rot_count)); + DONE; +}) + ;; Expanders for arithmetic shift left on each vector element (define_expand "vashl3" [(set (match_operand:VEC_I 0 "vint_operand") diff --git a/gcc/testsuite/gcc.target/powerpc/vec_rotate-1.c b/gcc/testsuite/gcc.target/powerpc/vec_rotate-1.c new file mode 100644 index 00000000000..f035a578292 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec_rotate-1.c @@ -0,0 +1,39 @@ +/* { dg-options "-O3" } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ + +/* Check vectorizer can exploit vector rotation instructions on Power, mainly + for the case rotation count is const number. + + Check for instructions vrlb/vrlh/vrlw only available if altivec supported. */ + +#define N 256 +unsigned int suw[N], ruw[N]; +unsigned short suh[N], ruh[N]; +unsigned char sub[N], rub[N]; + +void +testUW () +{ + for (int i = 0; i < 256; ++i) + ruw[i] = (suw[i] >> 8) | (suw[i] << (sizeof (suw[0]) * 8 - 8)); +} + +void +testUH () +{ + for (int i = 0; i < 256; ++i) + ruh[i] = (unsigned short) (suh[i] >> 9) + | (unsigned short) (suh[i] << (sizeof (suh[0]) * 8 - 9)); +} + +void +testUB () +{ + for (int i = 0; i < 256; ++i) + rub[i] = (unsigned char) (sub[i] >> 5) + | (unsigned char) (sub[i] << (sizeof (sub[0]) * 8 - 5)); +} + +/* { dg-final { scan-assembler {\mvrlw\M} } } */ +/* { dg-final { scan-assembler {\mvrlh\M} } } */ +/* { dg-final { scan-assembler {\mvrlb\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec_rotate-2.c b/gcc/testsuite/gcc.target/powerpc/vec_rotate-2.c new file mode 100644 index 00000000000..0a2a965ddcb --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec_rotate-2.c @@ -0,0 +1,19 @@ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-O3 -mdejagnu-cpu=power8" } */ + +/* Check vectorizer can exploit vector rotation instructions on Power8, mainly + for the case rotation count is const number. + + Check for vrld which is available on Power8 and above. */ + +#define N 256 +unsigned long long sud[N], rud[N]; + +void +testULL () +{ + for (int i = 0; i < 256; ++i) + rud[i] = (sud[i] >> 8) | (sud[i] << (sizeof (sud[0]) * 8 - 8)); +} + +/* { dg-final { scan-assembler {\mvrld\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec_rotate-3.c b/gcc/testsuite/gcc.target/powerpc/vec_rotate-3.c new file mode 100644 index 00000000000..5e90ae6fd63 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec_rotate-3.c @@ -0,0 +1,40 @@ +/* { dg-options "-O3" } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ + +/* Check vectorizer can exploit vector rotation instructions on Power, mainly + for the case rotation count isn't const number. + + Check for instructions vrlb/vrlh/vrlw only available if altivec supported. */ + +#define N 256 +unsigned int suw[N], ruw[N]; +unsigned short suh[N], ruh[N]; +unsigned char sub[N], rub[N]; +extern unsigned char rot_cnt; + +void +testUW () +{ + for (int i = 0; i < 256; ++i) + ruw[i] = (suw[i] >> rot_cnt) | (suw[i] << (sizeof (suw[0]) * 8 - rot_cnt)); +} + +void +testUH () +{ + for (int i = 0; i < 256; ++i) + ruh[i] = (unsigned short) (suh[i] >> rot_cnt) + | (unsigned short) (suh[i] << (sizeof (suh[0]) * 8 - rot_cnt)); +} + +void +testUB () +{ + for (int i = 0; i < 256; ++i) + rub[i] = (unsigned char) (sub[i] >> rot_cnt) + | (unsigned char) (sub[i] << (sizeof (sub[0]) * 8 - rot_cnt)); +} + +/* { dg-final { scan-assembler {\mvrlw\M} } } */ +/* { dg-final { scan-assembler {\mvrlh\M} } } */ +/* { dg-final { scan-assembler {\mvrlb\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec_rotate-4.c b/gcc/testsuite/gcc.target/powerpc/vec_rotate-4.c new file mode 100644 index 00000000000..0d3e8378ed6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec_rotate-4.c @@ -0,0 +1,20 @@ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-O3 -mdejagnu-cpu=power8" } */ + +/* Check vectorizer can exploit vector rotation instructions on Power8, mainly + for the case rotation count isn't const number. + + Check for vrld which is available on Power8 and above. */ + +#define N 256 +unsigned long long sud[N], rud[N]; +extern unsigned char rot_cnt; + +void +testULL () +{ + for (int i = 0; i < 256; ++i) + rud[i] = (sud[i] >> rot_cnt) | (sud[i] << (sizeof (sud[0]) * 8 - rot_cnt)); +} + +/* { dg-final { scan-assembler {\mvrld\M} } } */ --------------02F797A7C2E35F36F0E60D38--