[PATCH v4 0/4] When cmodel=extreme, add macro support and only support macros.

[PATCH v4 0/4] When cmodel=extreme, add macro support and only support macros.

[Lulu Cheng]

v3 -> v4:
  1. Add macro support for TLS symbols
  2. Added support for loading __get_tls_addr symbol address using call36.
  3. Merge template got_load_tls_{ld/gd/le/ie}.
  4. Enable explicit reloc for extreme TLS GD/LD with -mexplicit-relocs=auto.


v2 -> v3:
  1. Modify the detection rules of a test case.

v1 -> v2:
  1. Use the temporarily allocated registers as intermediate registers to implement the extreme macro.
  2. Fixed bugs in v1 test cases.


Lulu Cheng (4):
  LoongArch: Merge template got_load_tls_{ld/gd/le/ie}.
  LoongArch: Add the macro implementation of mcmodel=extreme.
  LoongArch: Enable explicit reloc for extreme TLS GD/LD with
    -mexplicit-relocs=auto.
  LoongArch: Added support for loading __get_tls_addr symbol address
    using call36.

 gcc/config/loongarch/loongarch-protos.h       |   1 +
 gcc/config/loongarch/loongarch.cc             | 182 +++++++++---------
 gcc/config/loongarch/loongarch.md             | 101 ++++++----
 gcc/config/loongarch/predicates.md            |  12 ++
 .../gcc.target/loongarch/attr-model-5.c       |   8 +
 .../explicit-relocs-extreme-auto-tls-ld-gd.c  |   5 +
 .../explicit-relocs-medium-auto-tls-ld-gd.c   |   5 +
 ...icit-relocs-medium-call36-auto-tls-ld-gd.c |   5 +
 .../loongarch/func-call-extreme-5.c           |   7 +
 .../loongarch/func-call-extreme-6.c           |   7 +
 .../gcc.target/loongarch/tls-extreme-macro.c  |  35 ++++
 11 files changed, 239 insertions(+), 129 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/attr-model-5.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/explicit-relocs-medium-auto-tls-ld-gd.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/explicit-relocs-medium-call36-auto-tls-ld-gd.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-extreme-5.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-extreme-6.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/tls-extreme-macro.c

-- 
2.39.3

[PATCH v4 1/4] LoongArch: Merge template got_load_tls_{ld/gd/le/ie}.

[Lulu Cheng]

gcc/ChangeLog:

	* config/loongarch/loongarch.cc (loongarch_load_tls):
	Load all types of tls symbols through one function.
	(loongarch_got_load_tls_gd): Delete.
	(loongarch_got_load_tls_ld): Delete.
	(loongarch_got_load_tls_ie): Delete.
	(loongarch_got_load_tls_le): Delete.
	(loongarch_call_tls_get_addr): Modify the called function name.
	(loongarch_legitimize_tls_address): Likewise.
	* config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
	(@load_tls<mode>): New template.
	(@got_load_tls_ld<mode>): Delete.
	(@got_load_tls_le<mode>): Delete.
	(@got_load_tls_ie<mode>): Delete.
---
 gcc/config/loongarch/loongarch.cc | 47 +++++-------------------
 gcc/config/loongarch/loongarch.md | 59 ++++++++++++-------------------
 2 files changed, 30 insertions(+), 76 deletions(-)

diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index dba1252c8f7..2f7de6f94d3 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -2736,36 +2736,12 @@ loongarch_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
 /* The __tls_get_attr symbol.  */
 static GTY (()) rtx loongarch_tls_symbol;
 
-/* Load an entry from the GOT for a TLS GD access.  */
+/* Load an entry for a TLS access.  */
 
 static rtx
-loongarch_got_load_tls_gd (rtx dest, rtx sym)
+loongarch_load_tls (rtx dest, rtx sym)
 {
-  return gen_got_load_tls_gd (Pmode, dest, sym);
-}
-
-/* Load an entry from the GOT for a TLS LD access.  */
-
-static rtx
-loongarch_got_load_tls_ld (rtx dest, rtx sym)
-{
-  return gen_got_load_tls_ld (Pmode, dest, sym);
-}
-
-/* Load an entry from the GOT for a TLS IE access.  */
-
-static rtx
-loongarch_got_load_tls_ie (rtx dest, rtx sym)
-{
-  return gen_got_load_tls_ie (Pmode, dest, sym);
-}
-
-/* Add in the thread pointer for a TLS LE access.  */
-
-static rtx
-loongarch_got_load_tls_le (rtx dest, rtx sym)
-{
-  return gen_got_load_tls_le (Pmode, dest, sym);
+  return gen_load_tls (Pmode, dest, sym);
 }
 
 /* Return an instruction sequence that calls __tls_get_addr.  SYM is
@@ -2809,14 +2785,7 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0)
 	emit_insn (gen_tls_low (Pmode, a0, high, loc));
     }
   else
-    {
-      if (type == SYMBOL_TLSLDM)
-	emit_insn (loongarch_got_load_tls_ld (a0, loc));
-      else if (type == SYMBOL_TLSGD)
-	emit_insn (loongarch_got_load_tls_gd (a0, loc));
-      else
-	gcc_unreachable ();
-    }
+    emit_insn (loongarch_load_tls (a0, loc));
 
   if (flag_plt)
     {
@@ -2953,10 +2922,10 @@ loongarch_legitimize_tls_address (rtx loc)
 	  /* la.tls.ie; tp-relative add.  */
 	  tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM);
 	  tmp1 = gen_reg_rtx (Pmode);
+	  tmp2 = loongarch_unspec_address (loc, SYMBOL_TLS_IE);
 	  dest = gen_reg_rtx (Pmode);
 	  if (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE)
 	    {
-	      tmp2 = loongarch_unspec_address (loc, SYMBOL_TLS_IE);
 	      tmp3 = gen_reg_rtx (Pmode);
 	      rtx high = gen_rtx_HIGH (Pmode, copy_rtx (tmp2));
 	      high = loongarch_force_temporary (tmp3, high);
@@ -2979,7 +2948,7 @@ loongarch_legitimize_tls_address (rtx loc)
 		emit_insn (gen_ld_from_got (Pmode, tmp1, high, tmp2));
 	    }
 	  else
-	    emit_insn (loongarch_got_load_tls_ie (tmp1, loc));
+	    emit_insn (loongarch_load_tls (tmp1, tmp2));
 	  emit_insn (gen_add3_insn (dest, tmp1, tp));
 	}
       break;
@@ -3011,11 +2980,11 @@ loongarch_legitimize_tls_address (rtx loc)
 
 	  tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM);
 	  tmp1 = gen_reg_rtx (Pmode);
+	  tmp2 = loongarch_unspec_address (loc, SYMBOL_TLS_LE);
 	  dest = gen_reg_rtx (Pmode);
 
 	  if (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE)
 	    {
-	      tmp2 = loongarch_unspec_address (loc, SYMBOL_TLS_LE);
 	      tmp3 = gen_reg_rtx (Pmode);
 	      rtx high = gen_rtx_HIGH (Pmode, copy_rtx (tmp2));
 	      high = loongarch_force_temporary (tmp3, high);
@@ -3043,7 +3012,7 @@ loongarch_legitimize_tls_address (rtx loc)
 		}
 	    }
 	  else
-	    emit_insn (loongarch_got_load_tls_le (tmp1, loc));
+	    emit_insn (loongarch_load_tls (tmp1, tmp2));
 	  emit_insn (gen_add3_insn (dest, tmp1, tp));
 	}
       break;
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index dda3cdf8be5..0b61b013798 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -51,10 +51,7 @@ (define_c_enum "unspec" [
   UNSPEC_BITREV_8B
 
   ;; TLS
-  UNSPEC_TLS_GD
-  UNSPEC_TLS_LD
-  UNSPEC_TLS_LE
-  UNSPEC_TLS_IE
+  UNSPEC_TLS
 
   ;; Stack tie
   UNSPEC_TIE
@@ -2701,45 +2698,33 @@ (define_insn "store_word<mode>"
 
 ;; Thread-Local Storage
 
-(define_insn "@got_load_tls_gd<mode>"
+(define_insn "@load_tls<mode>"
   [(set (match_operand:P 0 "register_operand" "=r")
 	(unspec:P
 	    [(match_operand:P 1 "symbolic_operand" "")]
-	    UNSPEC_TLS_GD))]
+	    UNSPEC_TLS))]
   ""
-  "la.tls.gd\t%0,%1"
-  [(set_attr "got" "load")
-   (set_attr "mode" "<MODE>")])
-
-(define_insn "@got_load_tls_ld<mode>"
-  [(set (match_operand:P 0 "register_operand" "=r")
-	(unspec:P
-	    [(match_operand:P 1 "symbolic_operand" "")]
-	    UNSPEC_TLS_LD))]
-  ""
-  "la.tls.ld\t%0,%1"
-  [(set_attr "got" "load")
-   (set_attr "mode" "<MODE>")])
+{
+  enum loongarch_symbol_type symbol_type;
+  gcc_assert (loongarch_symbolic_constant_p (operands[1], &symbol_type));
 
-(define_insn "@got_load_tls_le<mode>"
-  [(set (match_operand:P 0 "register_operand" "=r")
-	(unspec:P
-	    [(match_operand:P 1 "symbolic_operand" "")]
-	    UNSPEC_TLS_LE))]
-  ""
-  "la.tls.le\t%0,%1"
-  [(set_attr "got" "load")
-   (set_attr "mode" "<MODE>")])
+  switch (symbol_type)
+    {
+    case SYMBOL_TLS_LE:
+      return "la.tls.le\t%0,%1";
+    case SYMBOL_TLS_IE:
+      return "la.tls.ie\t%0,%1";
+    case SYMBOL_TLSLDM:
+      return "la.tls.ld\t%0,%1";
+    case SYMBOL_TLSGD:
+      return "la.tls.gd\t%0,%1";
 
-(define_insn "@got_load_tls_ie<mode>"
-  [(set (match_operand:P 0 "register_operand" "=r")
-	(unspec:P
-	    [(match_operand:P 1 "symbolic_operand" "")]
-	    UNSPEC_TLS_IE))]
-  ""
-  "la.tls.ie\t%0,%1"
-  [(set_attr "got" "load")
-   (set_attr "mode" "<MODE>")])
+    default:
+      gcc_unreachable ();
+    }
+}
+  [(set_attr "mode" "<MODE>")
+   (set_attr "length" "2")])
 
 ;; Move operand 1 to the high word of operand 0 using movgr2frh.w, preserving the
 ;; value in the low word.
-- 
2.39.3

Re: [PATCH v4 1/4] LoongArch: Merge template got_load_tls_{ld/gd/le/ie}.

[Xi Ruoyao]

On Fri, 2024-01-26 at 15:37 +0800, Lulu Cheng wrote:

> +(define_insn "@load_tls<mode>"
>    [(set (match_operand:P 0 "register_operand" "=r")
>  	(unspec:P
>  	    [(match_operand:P 1 "symbolic_operand" "")]
> -	    UNSPEC_TLS_GD))]
> +	    UNSPEC_TLS))]

/* snip */

> +{
> +  enum loongarch_symbol_type symbol_type;
> +  gcc_assert (loongarch_symbolic_constant_p (operands[1],
> &symbol_type));

/* snip */

> +  switch (symbol_type)
> +    {
> +    case SYMBOL_TLS_LE:
> +      return "la.tls.le\t%0,%1";
> +    case SYMBOL_TLS_IE:
> +      return "la.tls.ie\t%0,%1";
> +    case SYMBOL_TLSLDM:
> +      return "la.tls.ld\t%0,%1";
> +    case SYMBOL_TLSGD:
> +      return "la.tls.gd\t%0,%1";

/* snip */

> +    default:
> +      gcc_unreachable ();
> +    }
> +}
> +  [(set_attr "mode" "<MODE>")
> +   (set_attr "length" "2")])

Should be 8, it's in bytes.

-- 
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University

Re: [PATCH v4 1/4] LoongArch: Merge template got_load_tls_{ld/gd/le/ie}.

[chenglulu]

在 2024/1/26 下午4:52, Xi Ruoyao 写道:
> On Fri, 2024-01-26 at 15:37 +0800, Lulu Cheng wrote:
>
>> +(define_insn "@load_tls<mode>"
>>     [(set (match_operand:P 0 "register_operand" "=r")
>>   	(unspec:P
>>   	    [(match_operand:P 1 "symbolic_operand" "")]
>> -	    UNSPEC_TLS_GD))]
>> +	    UNSPEC_TLS))]
> /* snip */
>
>> +{
>> +  enum loongarch_symbol_type symbol_type;
>> +  gcc_assert (loongarch_symbolic_constant_p (operands[1],
>> &symbol_type));
> /* snip */
>
>> +  switch (symbol_type)
>> +    {
>> +    case SYMBOL_TLS_LE:
>> +      return "la.tls.le\t%0,%1";
>> +    case SYMBOL_TLS_IE:
>> +      return "la.tls.ie\t%0,%1";
>> +    case SYMBOL_TLSLDM:
>> +      return "la.tls.ld\t%0,%1";
>> +    case SYMBOL_TLSGD:
>> +      return "la.tls.gd\t%0,%1";
> /* snip */
>
>> +    default:
>> +      gcc_unreachable ();
>> +    }
>> +}
>> +  [(set_attr "mode" "<MODE>")
>> +   (set_attr "length" "2")])
> Should be 8, it's in bytes.
>
Um, sorry, I meant to use insn_count.

Re: [PATCH v4 1/4] LoongArch: Merge template got_load_tls_{ld/gd/le/ie}.

[chenglulu]

在 2024/1/26 下午4:59, chenglulu 写道:
>
> 在 2024/1/26 下午4:52, Xi Ruoyao 写道:
>> On Fri, 2024-01-26 at 15:37 +0800, Lulu Cheng wrote:
>>
>>> +(define_insn "@load_tls<mode>"
>>>     [(set (match_operand:P 0 "register_operand" "=r")
>>>       (unspec:P
>>>           [(match_operand:P 1 "symbolic_operand" "")]
>>> -        UNSPEC_TLS_GD))]
>>> +        UNSPEC_TLS))]
>> /* snip */
>>
>>> +{
>>> +  enum loongarch_symbol_type symbol_type;
>>> +  gcc_assert (loongarch_symbolic_constant_p (operands[1],
>>> &symbol_type));
>> /* snip */
>>
>>> +  switch (symbol_type)
>>> +    {
>>> +    case SYMBOL_TLS_LE:
>>> +      return "la.tls.le\t%0,%1";
>>> +    case SYMBOL_TLS_IE:
>>> +      return "la.tls.ie\t%0,%1";
>>> +    case SYMBOL_TLSLDM:
>>> +      return "la.tls.ld\t%0,%1";
>>> +    case SYMBOL_TLSGD:
>>> +      return "la.tls.gd\t%0,%1";
>> /* snip */
>>
>>> +    default:
>>> +      gcc_unreachable ();
>>> +    }
>>> +}
>>> +  [(set_attr "mode" "<MODE>")
>>> +   (set_attr "length" "2")])
When the symbol type is TLS LE and -mcmodel=extreme, 4 instructions are 
generated here, and I will also modify them here.

>> Should be 8, it's in bytes.
>>
> Um, sorry, I meant to use insn_count.

[PATCH v4 2/4] LoongArch: Add the macro implementation of mcmodel=extreme.

[Lulu Cheng]

gcc/ChangeLog:

	* config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
	Add function declaration.
	* config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
	For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
	is not allowed
	(loongarch_load_tls): Added macro support in extreme mode.
	(loongarch_call_tls_get_addr): Likewise.
	(loongarch_legitimize_tls_address): Likewise.
	(loongarch_force_address): Likewise.
	(loongarch_legitimize_move): Likewise.
	(loongarch_output_mi_thunk): Likewise.
	(loongarch_option_override_internal): Remove the code that detects
	explicit relocs status.
	(loongarch_handle_model_attribute): Likewise.
	* config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
	* config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
	(symbolic_off64_or_reg_operand): Likewise.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/attr-model-5.c: New test.
	* gcc.target/loongarch/func-call-extreme-5.c: New test.
	* gcc.target/loongarch/func-call-extreme-6.c: New test.
	* gcc.target/loongarch/tls-extreme-macro.c: New test.
---
 gcc/config/loongarch/loongarch-protos.h       |   1 +
 gcc/config/loongarch/loongarch.cc             | 108 +++++++++++-------
 gcc/config/loongarch/loongarch.md             |  42 +++++++
 gcc/config/loongarch/predicates.md            |  12 ++
 .../gcc.target/loongarch/attr-model-5.c       |   8 ++
 .../loongarch/func-call-extreme-5.c           |   7 ++
 .../loongarch/func-call-extreme-6.c           |   7 ++
 .../gcc.target/loongarch/tls-extreme-macro.c  |  35 ++++++
 8 files changed, 177 insertions(+), 43 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/attr-model-5.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-extreme-5.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/func-call-extreme-6.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/tls-extreme-macro.c

diff --git a/gcc/config/loongarch/loongarch-protos.h b/gcc/config/loongarch/loongarch-protos.h
index 9ffc92afead..1fdfda9af01 100644
--- a/gcc/config/loongarch/loongarch-protos.h
+++ b/gcc/config/loongarch/loongarch-protos.h
@@ -222,4 +222,5 @@ extern rtx loongarch_build_signbit_mask (machine_mode, bool, bool);
 extern void loongarch_emit_swrsqrtsf (rtx, rtx, machine_mode, bool);
 extern void loongarch_emit_swdivsf (rtx, rtx, rtx, machine_mode);
 extern bool loongarch_explicit_relocs_p (enum loongarch_symbol_type);
+extern bool loongarch_symbol_extreme_p (enum loongarch_symbol_type);
 #endif /* ! GCC_LOONGARCH_PROTOS_H */
diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index 2f7de6f94d3..4c64742f78b 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -1935,8 +1935,13 @@ loongarch_symbolic_constant_p (rtx x, enum loongarch_symbol_type *symbol_type)
      relocations.  */
   switch (*symbol_type)
     {
-    case SYMBOL_PCREL:
     case SYMBOL_PCREL64:
+      /* When the code model is extreme, the non-zero offset situation
+	 has not been handled well, so it is disabled here now.  */
+      if (!loongarch_explicit_relocs_p (SYMBOL_PCREL64))
+	return false;
+    /* fall through */
+    case SYMBOL_PCREL:
       /* GAS rejects offsets outside the range [-2^31, 2^31-1].  */
       return sext_hwi (INTVAL (offset), 32) == INTVAL (offset);
 
@@ -2739,9 +2744,15 @@ static GTY (()) rtx loongarch_tls_symbol;
 /* Load an entry for a TLS access.  */
 
 static rtx
-loongarch_load_tls (rtx dest, rtx sym)
+loongarch_load_tls (rtx dest, rtx sym, enum loongarch_symbol_type type)
 {
-  return gen_load_tls (Pmode, dest, sym);
+  /* TLS LE gets a 32 or 64 bit offset here, so one register can do it.  */
+  if (type == SYMBOL_TLS_LE)
+    return gen_load_tls (Pmode, dest, sym);
+
+  return loongarch_symbol_extreme_p (type) ?
+    gen_movdi_symbolic_off64 (dest, sym, gen_reg_rtx (DImode))
+    : gen_load_tls (Pmode, dest, sym);
 }
 
 /* Return an instruction sequence that calls __tls_get_addr.  SYM is
@@ -2773,8 +2784,6 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0)
 
       if (TARGET_CMODEL_EXTREME)
 	{
-	  gcc_assert (TARGET_EXPLICIT_RELOCS);
-
 	  rtx tmp1 = gen_reg_rtx (Pmode);
 	  emit_insn (gen_tls_low (Pmode, tmp1, gen_rtx_REG (Pmode, 0), loc));
 	  emit_insn (gen_lui_h_lo20 (tmp1, tmp1, loc));
@@ -2785,7 +2794,7 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0)
 	emit_insn (gen_tls_low (Pmode, a0, high, loc));
     }
   else
-    emit_insn (loongarch_load_tls (a0, loc));
+    emit_insn (loongarch_load_tls (a0, loc, type));
 
   if (flag_plt)
     {
@@ -2852,22 +2861,26 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0)
 
 	case CMODEL_EXTREME:
 	    {
-	      gcc_assert (TARGET_EXPLICIT_RELOCS);
-
-	      rtx tmp1 = gen_reg_rtx (Pmode);
-	      rtx high = gen_reg_rtx (Pmode);
-
-	      loongarch_emit_move (high,
-				   gen_rtx_HIGH (Pmode, loongarch_tls_symbol));
-	      loongarch_emit_move (tmp1, gen_rtx_LO_SUM (Pmode,
-							 gen_rtx_REG (Pmode, 0),
-							 loongarch_tls_symbol));
-	      emit_insn (gen_lui_h_lo20 (tmp1, tmp1, loongarch_tls_symbol));
-	      emit_insn (gen_lui_h_hi12 (tmp1, tmp1, loongarch_tls_symbol));
-	      loongarch_emit_move (dest,
-				   gen_rtx_MEM (Pmode,
-						gen_rtx_PLUS (Pmode,
-							      high, tmp1)));
+	      if (loongarch_explicit_relocs_p (SYMBOL_GOT_DISP))
+		{
+		  rtx tmp1 = gen_reg_rtx (Pmode);
+		  rtx high = gen_reg_rtx (Pmode);
+
+		  loongarch_emit_move (high,
+				       gen_rtx_HIGH (Pmode, loongarch_tls_symbol));
+		  loongarch_emit_move (tmp1, gen_rtx_LO_SUM (Pmode,
+							     gen_rtx_REG (Pmode, 0),
+							     loongarch_tls_symbol));
+		  emit_insn (gen_lui_h_lo20 (tmp1, tmp1, loongarch_tls_symbol));
+		  emit_insn (gen_lui_h_hi12 (tmp1, tmp1, loongarch_tls_symbol));
+		  loongarch_emit_move (dest,
+				       gen_rtx_MEM (Pmode,
+						    gen_rtx_PLUS (Pmode,
+								  high, tmp1)));
+		}
+	      else
+	       emit_insn (gen_movdi_symbolic_off64 (dest, loongarch_tls_symbol,
+						 gen_reg_rtx (DImode)));
 	    }
 	  break;
 
@@ -2932,8 +2945,6 @@ loongarch_legitimize_tls_address (rtx loc)
 
 	      if (TARGET_CMODEL_EXTREME)
 		{
-		  gcc_assert (TARGET_EXPLICIT_RELOCS);
-
 		  rtx tmp3 = gen_reg_rtx (Pmode);
 		  emit_insn (gen_tls_low (Pmode, tmp3,
 					  gen_rtx_REG (Pmode, 0), tmp2));
@@ -2948,7 +2959,7 @@ loongarch_legitimize_tls_address (rtx loc)
 		emit_insn (gen_ld_from_got (Pmode, tmp1, high, tmp2));
 	    }
 	  else
-	    emit_insn (loongarch_load_tls (tmp1, tmp2));
+	    emit_insn (loongarch_load_tls (tmp1, tmp2, SYMBOL_TLS_IE));
 	  emit_insn (gen_add3_insn (dest, tmp1, tp));
 	}
       break;
@@ -3005,14 +3016,12 @@ loongarch_legitimize_tls_address (rtx loc)
 
 	      if (TARGET_CMODEL_EXTREME)
 		{
-		  gcc_assert (TARGET_EXPLICIT_RELOCS);
-
 		  emit_insn (gen_lui_h_lo20 (tmp1, tmp1, tmp2));
 		  emit_insn (gen_lui_h_hi12 (tmp1, tmp1, tmp2));
 		}
 	    }
 	  else
-	    emit_insn (loongarch_load_tls (tmp1, tmp2));
+	    emit_insn (loongarch_load_tls (tmp1, tmp2, SYMBOL_TLS_LE));
 	  emit_insn (gen_add3_insn (dest, tmp1, tp));
 	}
       break;
@@ -3085,7 +3094,7 @@ loongarch_force_address (rtx x, machine_mode mode)
   return x;
 }
 
-static bool
+bool
 loongarch_symbol_extreme_p (enum loongarch_symbol_type type)
 {
   switch (type)
@@ -3363,6 +3372,21 @@ loongarch_legitimize_move (machine_mode mode, rtx dest, rtx src)
       return true;
     }
 
+  /* Obtain the address of the symbol through the macro instruction
+     of two registers.  */
+  enum loongarch_symbol_type symbol_type;
+  if (TARGET_64BIT && register_operand (dest, mode)
+      && loongarch_symbolic_constant_p (src, &symbol_type)
+      && loongarch_symbol_extreme_p (symbol_type))
+    {
+      gcc_assert (can_create_pseudo_p ());
+      rtx tmp_reg = gen_reg_rtx (DImode);
+      emit_insn (gen_movdi_symbolic_off64 (dest, src, tmp_reg));
+      set_unique_reg_note (get_last_insn (), REG_UNUSED, tmp_reg);
+      set_unique_reg_note (get_last_insn (), REG_EQUAL, src);
+      return true;
+    }
+
   return false;
 }
 
@@ -7419,12 +7443,22 @@ loongarch_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
      allowed, otherwise load the address into a register first.  */
   if (use_sibcall_p)
     {
-      insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
+      if (TARGET_CMODEL_EXTREME)
+	{
+	  emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
+	  insn = emit_call_insn (gen_sibcall_internal (temp1, const0_rtx));
+	}
+      else
+	insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
       SIBLING_CALL_P (insn) = 1;
     }
   else
     {
-      loongarch_emit_move (temp1, fnaddr);
+      if (TARGET_CMODEL_EXTREME)
+	emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
+      else
+	loongarch_emit_move (temp1, fnaddr);
+
       emit_jump_insn (gen_indirect_jump (temp1));
     }
 
@@ -7529,10 +7563,6 @@ loongarch_option_override_internal (struct gcc_options *opts,
   switch (la_target.cmodel)
     {
       case CMODEL_EXTREME:
-	if (la_opt_explicit_relocs == EXPLICIT_RELOCS_NONE)
-	  error ("code model %qs is not compatible with %s",
-		 "extreme", "-mexplicit-relocs=none");
-
 	if (opts->x_flag_plt)
 	  {
 	    if (global_options_set.x_flag_plt)
@@ -7950,14 +7980,6 @@ loongarch_handle_model_attribute (tree *node, tree name, tree arg, int,
 	  *no_add_attrs = true;
 	  return NULL_TREE;
 	}
-      if (la_opt_explicit_relocs == EXPLICIT_RELOCS_NONE)
-	{
-	  error_at (DECL_SOURCE_LOCATION (decl),
-		    "%qE attribute is not compatible with %s", name,
-		    "-mexplicit-relocs=none");
-	  *no_add_attrs = true;
-	  return NULL_TREE;
-	}
 
       arg = TREE_VALUE (arg);
       if (TREE_CODE (arg) != STRING_CST)
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index 0b61b013798..5a2b181716a 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -82,6 +82,8 @@ (define_c_enum "unspec" [
 
   UNSPEC_SIBCALL_VALUE_MULTIPLE_INTERNAL_1
   UNSPEC_CALL_VALUE_MULTIPLE_INTERNAL_1
+
+  UNSPEC_LOAD_SYMBOL_OFFSET64
 ])
 
 (define_c_enum "unspecv" [
@@ -2182,6 +2184,46 @@ (define_insn_and_split "*movdi_64bit"
   [(set_attr "move_type" "move,const,load,store,mgtf,fpload,mftg,fpstore")
    (set_attr "mode" "DI")])
 
+;; Use two registers to get the global symbol address from the got table.
+;; la.global rd, rt, sym
+
+(define_insn_and_split "movdi_symbolic_off64"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+       (match_operand:DI 1 "symbolic_off64_or_reg_operand" "Yd,r"))
+  (unspec:DI [(const_int 0)]
+    UNSPEC_LOAD_SYMBOL_OFFSET64)
+  (clobber (match_operand:DI 2 "register_operand" "=&r,r"))]
+ "TARGET_64BIT && TARGET_CMODEL_EXTREME"
+{
+  if (which_alternative == 1)
+    return "#";
+
+  enum loongarch_symbol_type symbol_type;
+  gcc_assert (loongarch_symbolic_constant_p (operands[1], &symbol_type));
+
+  switch (symbol_type)
+    {
+    case SYMBOL_PCREL64:
+      return "la.local\t%0,%2,%1";
+    case SYMBOL_GOT_DISP:
+      return "la.global\t%0,%2,%1";
+    case SYMBOL_TLS_IE:
+      return "la.tls.ie\t%0,%2,%1";
+    case SYMBOL_TLSGD:
+      return "la.tls.gd\t%0,%2,%1";
+    case SYMBOL_TLSLDM:
+      return "la.tls.ld\t%0,%2,%1";
+
+    default:
+      gcc_unreachable ();
+  }
+}
+ "&& REG_P (operands[1]) && find_reg_note (insn, REG_UNUSED, operands[2]) != 0"
+ [(set (match_dup 0) (match_dup 1))]
+ ""
+ [(set_attr "mode" "DI")
+  (set_attr "length" "5")])
+
 ;; 32-bit Integer moves
 
 (define_expand "movsi"
diff --git a/gcc/config/loongarch/predicates.md b/gcc/config/loongarch/predicates.md
index 01aad8dc631..eba7f246c84 100644
--- a/gcc/config/loongarch/predicates.md
+++ b/gcc/config/loongarch/predicates.md
@@ -576,6 +576,18 @@ (define_predicate "mem_simple_ldst_operand"
 	  || symbolic_pcrel_offset_operand (op, Pmode));
 })
 
+(define_predicate "symbolic_off64_operand"
+ (match_code "const,symbol_ref,label_ref")
+{
+  enum loongarch_symbol_type type;
+  return loongarch_symbolic_constant_p (op, &type)
+	 && loongarch_symbol_extreme_p (type);
+})
+
+(define_predicate "symbolic_off64_or_reg_operand"
+ (ior (match_operand 0 "register_operand")
+      (match_operand 0 "symbolic_off64_operand")))
+
 (define_predicate "equality_operator"
   (match_code "eq,ne"))
 
diff --git a/gcc/testsuite/gcc.target/loongarch/attr-model-5.c b/gcc/testsuite/gcc.target/loongarch/attr-model-5.c
new file mode 100644
index 00000000000..5f2c3ec9e44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/attr-model-5.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-mexplicit-relocs=none -mcmodel=extreme -O2 -fno-pic" } */
+/* { dg-final { scan-assembler "la.local\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,x" } } */
+/* { dg-final { scan-assembler "la.local\t\\\$r\[0-9\]+,y" } } */
+/* { dg-final { scan-assembler "la.local\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,counter" } } */
+
+#define ATTR_MODEL_TEST
+#include "attr-model-test.c"
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-5.c b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-5.c
new file mode 100644
index 00000000000..b1bd9d236ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-5.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs=none -mcmodel=extreme" } */
+/* { dg-final { scan-assembler "test:.*la.global\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,g" } } */
+/* { dg-final { scan-assembler "test1:.*la.global\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,f" } } */
+/* { dg-final { scan-assembler "test2:.*la.local\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,l" } } */
+
+#include "func-call-extreme-1.c"
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-6.c b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-6.c
new file mode 100644
index 00000000000..6e6ad5c9f5c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-6.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs=none -mcmodel=extreme" } */
+/* { dg-final { scan-assembler "test:.*la.global\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,g" } } */
+/* { dg-final { scan-assembler "test1:.*la.local\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,f" } } */
+/* { dg-final { scan-assembler "test2:.*la.local\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,l" } } */
+
+#include "func-call-extreme-1.c"
diff --git a/gcc/testsuite/gcc.target/loongarch/tls-extreme-macro.c b/gcc/testsuite/gcc.target/loongarch/tls-extreme-macro.c
new file mode 100644
index 00000000000..4341f82129c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/tls-extreme-macro.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O2 -mcmodel=extreme -fno-plt -mexplicit-relocs=none" } */
+/* { dg-final { scan-assembler "test_le:.*la.tls.le\t\\\$r\[0-9\]+,\\\.L" { target tls_native } } } */
+/* { dg-final { scan-assembler "test_ie:.*la.tls.ie\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,\\\.L" { target tls_native } } } */
+/* { dg-final { scan-assembler "test_ld:.*la.tls.ld\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,\\\.L.*la.global\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,__tls_get_addr" { target tls_native } } } */
+/* { dg-final { scan-assembler "test_le:.*la.tls.gd\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,\\\.L.*la.global\t\\\$r\[0-9\]+,\\\$r\[0-9\]+,__tls_get_addr" { target tls_native } } } */
+
+__thread int c __attribute__ ((tls_model ("local-exec")));
+__thread int d __attribute__ ((tls_model ("initial-exec")));
+__thread int e __attribute__ ((tls_model ("local-dynamic")));
+__thread int f __attribute__ ((tls_model ("global-dynamic")));
+
+int
+test_le (void)
+{
+  return c;
+}
+
+int
+test_ie (void)
+{
+  return d;
+}
+
+int
+test_ld (void)
+{
+  return e;
+}
+
+int
+test_gd (void)
+{
+  return f;
+}
-- 
2.39.3

Re: [PATCH v4 2/4] LoongArch: Add the macro implementation of mcmodel=extreme.

[Xi Ruoyao]

On Fri, 2024-01-26 at 15:37 +0800, Lulu Cheng wrote:
> +;; Use two registers to get the global symbol address from the got table.
> +;; la.global rd, rt, sym
> +
> +(define_insn_and_split "movdi_symbolic_off64"
> + [(set (match_operand:DI 0 "register_operand" "=r,r")
> +       (match_operand:DI 1 "symbolic_off64_or_reg_operand" "Yd,r"))
> +  (unspec:DI [(const_int 0)]
> +    UNSPEC_LOAD_SYMBOL_OFFSET64)
> +  (clobber (match_operand:DI 2 "register_operand" "=&r,r"))]
> + "TARGET_64BIT && TARGET_CMODEL_EXTREME"
> +{
> +  if (which_alternative == 1)
> +    return "#";
> +
> +  enum loongarch_symbol_type symbol_type;
> +  gcc_assert (loongarch_symbolic_constant_p (operands[1], &symbol_type));
> +
> +  switch (symbol_type)
> +    {
> +    case SYMBOL_PCREL64:
> +      return "la.local\t%0,%2,%1";
> +    case SYMBOL_GOT_DISP:
> +      return "la.global\t%0,%2,%1";
> +    case SYMBOL_TLS_IE:
> +      return "la.tls.ie\t%0,%2,%1";
> +    case SYMBOL_TLSGD:
> +      return "la.tls.gd\t%0,%2,%1";
> +    case SYMBOL_TLSLDM:
> +      return "la.tls.ld\t%0,%2,%1";
> +
> +    default:
> +      gcc_unreachable ();
> +  }
> +}
> + "&& REG_P (operands[1]) && find_reg_note (insn, REG_UNUSED, operands[2]) != 0"
> + [(set (match_dup 0) (match_dup 1))]
> + ""
> + [(set_attr "mode" "DI")
> +  (set_attr "length" "5")])

Should be 20, in bytes.

-- 
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University

[PATCH v4 3/4] LoongArch: Enable explicit reloc for extreme TLS GD/LD with -mexplicit-relocs=auto.

[Lulu Cheng]

Binutils does not support relaxation using four instructions to obtain
symbol addresses

gcc/ChangeLog:

	* config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
	When the code model of the symbol is extreme and -mexplicit-relocs=auto,
	the macro instruction loading symbol address is not applicable.
	(loongarch_call_tls_get_addr): Adjust code.
	(loongarch_legitimize_tls_address): Likewise.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c: New test.
	* gcc.target/loongarch/explicit-relocs-medium-auto-tls-ld-gd.c: New test.
---
 gcc/config/loongarch/loongarch.cc             | 19 +++++++++----------
 .../explicit-relocs-extreme-auto-tls-ld-gd.c  |  5 +++++
 .../explicit-relocs-medium-auto-tls-ld-gd.c   |  5 +++++
 3 files changed, 19 insertions(+), 10 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/explicit-relocs-medium-auto-tls-ld-gd.c

diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index 4c64742f78b..b76e201c0ef 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -1971,6 +1971,10 @@ loongarch_explicit_relocs_p (enum loongarch_symbol_type type)
   if (la_opt_explicit_relocs != EXPLICIT_RELOCS_AUTO)
     return la_opt_explicit_relocs == EXPLICIT_RELOCS_ALWAYS;
 
+  /* The linker don't know how to relax accesses in extreme code model.  */
+  if (loongarch_symbol_extreme_p (type))
+    return true;
+
   switch (type)
     {
       case SYMBOL_TLS_IE:
@@ -1982,11 +1986,6 @@ loongarch_explicit_relocs_p (enum loongarch_symbol_type type)
 	   does not relax 64-bit pc-relative accesses as at now.  */
 	return true;
       case SYMBOL_GOT_DISP:
-	/* The linker don't know how to relax GOT accesses in extreme
-	   code model.  */
-	if (TARGET_CMODEL_EXTREME)
-	  return true;
-
 	/* If we are performing LTO for a final link, and we have the
 	   linker plugin so we know the resolution of the symbols, then
 	   all GOT references are binding to external symbols or
@@ -2776,7 +2775,7 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0)
 
   start_sequence ();
 
-  if (la_opt_explicit_relocs == EXPLICIT_RELOCS_ALWAYS)
+  if (loongarch_explicit_relocs_p (type))
     {
       /* Split tls symbol to high and low.  */
       rtx high = gen_rtx_HIGH (Pmode, copy_rtx (loc));
@@ -2809,7 +2808,7 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0)
 	case CMODEL_MEDIUM:
 	    {
 	      rtx reg = gen_reg_rtx (Pmode);
-	      if (TARGET_EXPLICIT_RELOCS)
+	      if (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE)
 		{
 		  emit_insn (gen_pcalau12i (Pmode, reg, loongarch_tls_symbol));
 		  rtx call = gen_call_value_internal_1 (Pmode, v0, reg,
@@ -2845,7 +2844,7 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0)
 	case CMODEL_NORMAL:
 	case CMODEL_MEDIUM:
 	    {
-	      if (TARGET_EXPLICIT_RELOCS)
+	      if (loongarch_explicit_relocs_p (SYMBOL_GOT_DISP))
 		{
 		  rtx high = gen_reg_rtx (Pmode);
 		  loongarch_emit_move (high,
@@ -2937,7 +2936,7 @@ loongarch_legitimize_tls_address (rtx loc)
 	  tmp1 = gen_reg_rtx (Pmode);
 	  tmp2 = loongarch_unspec_address (loc, SYMBOL_TLS_IE);
 	  dest = gen_reg_rtx (Pmode);
-	  if (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE)
+	  if (loongarch_explicit_relocs_p (SYMBOL_TLS_IE))
 	    {
 	      tmp3 = gen_reg_rtx (Pmode);
 	      rtx high = gen_rtx_HIGH (Pmode, copy_rtx (tmp2));
@@ -2994,7 +2993,7 @@ loongarch_legitimize_tls_address (rtx loc)
 	  tmp2 = loongarch_unspec_address (loc, SYMBOL_TLS_LE);
 	  dest = gen_reg_rtx (Pmode);
 
-	  if (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE)
+	  if (loongarch_explicit_relocs_p (SYMBOL_TLS_LE))
 	    {
 	      tmp3 = gen_reg_rtx (Pmode);
 	      rtx high = gen_rtx_HIGH (Pmode, copy_rtx (tmp2));
diff --git a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c
new file mode 100644
index 00000000000..27baf4886d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fPIC -mexplicit-relocs=auto -mcmodel=extreme -fno-plt" } */
+/* { dg-final { scan-assembler-not "la.tls.[lg]d" { target tls_native } } } */
+
+#include "./explicit-relocs-auto-tls-ld-gd.c"
diff --git a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-medium-auto-tls-ld-gd.c b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-medium-auto-tls-ld-gd.c
new file mode 100644
index 00000000000..47bffae8af7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-medium-auto-tls-ld-gd.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fPIC -mexplicit-relocs=auto -mcmodel=medium -fplt" } */
+/* { dg-final { scan-assembler-not "la.global" { target tls_native } } } */
+
+#include "./explicit-relocs-auto-tls-ld-gd.c"
-- 
2.39.3

[PATCH v4 4/4] LoongArch: Added support for loading __get_tls_addr symbol address using call36.

[Lulu Cheng]

gcc/ChangeLog:

	* config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
	Add support for call36.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/explicit-relocs-medium-call36-auto-tls-ld-gd.c: New test.
---
 gcc/config/loongarch/loongarch.cc             | 20 +++++++++++++------
 ...icit-relocs-medium-call36-auto-tls-ld-gd.c |  5 +++++
 2 files changed, 19 insertions(+), 6 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/explicit-relocs-medium-call36-auto-tls-ld-gd.c

diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index b76e201c0ef..19bb37b0c04 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -2807,17 +2807,25 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0)
 
 	case CMODEL_MEDIUM:
 	    {
-	      rtx reg = gen_reg_rtx (Pmode);
 	      if (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE)
 		{
-		  emit_insn (gen_pcalau12i (Pmode, reg, loongarch_tls_symbol));
-		  rtx call = gen_call_value_internal_1 (Pmode, v0, reg,
-							loongarch_tls_symbol,
-							const0_rtx);
-		  insn = emit_call_insn (call);
+		  rtx call;
+
+		 if (HAVE_AS_SUPPORT_CALL36)
+		   call = gen_call_value_internal (v0, loongarch_tls_symbol, const0_rtx);
+		 else
+		   {
+		     rtx reg = gen_reg_rtx (Pmode);
+		     emit_insn (gen_pcalau12i (Pmode, reg, loongarch_tls_symbol));
+		     call = gen_call_value_internal_1 (Pmode, v0, reg,
+						       loongarch_tls_symbol,
+						       const0_rtx);
+		   }
+		 insn = emit_call_insn (call);
 		}
 	      else
 		{
+		  rtx reg = gen_reg_rtx (Pmode);
 		  emit_move_insn (reg, loongarch_tls_symbol);
 		  insn = emit_call_insn (gen_call_value_internal (v0,
 								  reg,
diff --git a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-medium-call36-auto-tls-ld-gd.c b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-medium-call36-auto-tls-ld-gd.c
new file mode 100644
index 00000000000..d1a4820834c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-medium-call36-auto-tls-ld-gd.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fPIC -mexplicit-relocs=auto -mcmodel=medium -fplt" } */
+/* { dg-final { scan-assembler "pcaddu18i\t\\\$r1,%call36\\\(__tls_get_addr\\\)" { target { tls_native && loongarch_call36_support } } } } */
+
+#include "./explicit-relocs-auto-tls-ld-gd.c"
-- 
2.39.3

Re: [PATCH v4 0/4] When cmodel=extreme, add macro support and only support macros.

[Xi Ruoyao]

[-- Attachment #1: Type: text/plain, Size: 650 bytes --]

On Fri, 2024-01-26 at 15:37 +0800, Lulu Cheng wrote:
> v3 -> v4:
>   1. Add macro support for TLS symbols
>   2. Added support for loading __get_tls_addr symbol address using call36.
>   3. Merge template got_load_tls_{ld/gd/le/ie}.
>   4. Enable explicit reloc for extreme TLS GD/LD with -mexplicit-relocs=auto.

I've rebased and attached the patch to fix the bad split in -mexplicit-
relocs={always,auto} -mcmodel=extreme on top of this series.  I've not
tested it seriously though (only tested the added and modified test
cases).

-- 
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University

[-- Attachment #2: 0001-LoongArch-Don-t-split-the-instructions-containing-re.patch --]
[-- Type: text/x-patch, Size: 16448 bytes --]

From 87c9eafd88ae4a4339e094af08c77e7dfc9ea700 Mon Sep 17 00:00:00 2001
From: Xi Ruoyao <xry111@xry111.site>
Date: Fri, 5 Jan 2024 18:40:06 +0800
Subject: [PATCH] LoongArch: Don't split the instructions containing relocs for
 extreme code model

The ABI mandates the pcalau12i/addi.d/lu32i.d/lu52i.d instructions for
addressing a symbol to be adjacent.  So model them as "one large
instruction", i.e. define_insn, with two output registers.  The real
address is the sum of these two registers.

The advantage of this approach is the RTL passes can still use ldx/stx
instructions to skip an addi.d instruction.

gcc/ChangeLog:

	* config/loongarch/loongarch.md (unspec): Add
	UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
	(la_pcrel64_two_parts): New define_insn.
	* config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
	typo in the comment.
	(loongarch_call_tls_get_addr): If -mcmodel=extreme
	-mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
	addressing the TLS symbol and __tls_get_addr.  Emit an REG_EQUAL
	note to allow CSE addressing __tls_get_addr.
	(loongarch_legitimize_tls_address): If -mcmodel=extreme
	-mexplicit-relocs={always,auto}, address TLS IE symbols with
	la_pcrel64_two_parts.
	(loongarch_split_symbol): If -mcmodel=extreme
	-mexplicit-relocs={always,auto}, address symbols with
	la_pcrel64_two_parts.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/func-call-extreme-1.c (dg-options):
	Use -O2 instead of -O0 to ensure the pcalau12i/addi/lu32i/lu52i
	instruction sequences are not reordered by the compiler.
	(NOIPA): Disallow interprocedural optimizations.
	* gcc.target/loongarch/func-call-extreme-2.c: Remove the content
	duplicated from func-call-extreme-1.c, include it instead.
	(dg-options): Likewise.
	* gcc.target/loongarch/func-call-extreme-3.c (dg-options):
	Likewise.
	* gcc.target/loongarch/func-call-extreme-4.c (dg-options):
	Likewise.
	* gcc.target/loongarch/cmodel-extreme-1.c: New test.
	* gcc.target/loongarch/cmodel-extreme-2.c: New test.
---
 gcc/config/loongarch/loongarch.cc             | 112 ++++++++++--------
 gcc/config/loongarch/loongarch.md             |  20 ++++
 .../gcc.target/loongarch/cmodel-extreme-1.c   |  18 +++
 .../gcc.target/loongarch/cmodel-extreme-2.c   |   7 ++
 .../loongarch/func-call-extreme-1.c           |  14 ++-
 .../loongarch/func-call-extreme-2.c           |  29 +----
 .../loongarch/func-call-extreme-3.c           |   2 +-
 .../loongarch/func-call-extreme-4.c           |   2 +-
 8 files changed, 122 insertions(+), 82 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/cmodel-extreme-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/cmodel-extreme-2.c

diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index 481903147b8..e70ce80c7b3 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -2737,7 +2737,7 @@ loongarch_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
   return plus_constant (Pmode, reg, offset);
 }
 
-/* The __tls_get_attr symbol.  */
+/* The __tls_get_addr symbol.  */
 static GTY (()) rtx loongarch_tls_symbol;
 
 /* Load an entry for a TLS access.  */
@@ -2777,20 +2777,22 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0)
 
   if (loongarch_explicit_relocs_p (type))
     {
-      /* Split tls symbol to high and low.  */
-      rtx high = gen_rtx_HIGH (Pmode, copy_rtx (loc));
-      high = loongarch_force_temporary (tmp, high);
-
       if (TARGET_CMODEL_EXTREME)
 	{
-	  rtx tmp1 = gen_reg_rtx (Pmode);
-	  emit_insn (gen_tls_low (Pmode, tmp1, gen_rtx_REG (Pmode, 0), loc));
-	  emit_insn (gen_lui_h_lo20 (tmp1, tmp1, loc));
-	  emit_insn (gen_lui_h_hi12 (tmp1, tmp1, loc));
-	  emit_move_insn (a0, gen_rtx_PLUS (Pmode, high, tmp1));
+	  rtx part1 = gen_reg_rtx (Pmode);
+	  rtx part2 = gen_reg_rtx (Pmode);
+
+	  emit_insn (gen_la_pcrel64_two_parts (part1, part2, loc));
+	  emit_move_insn (a0, gen_rtx_PLUS (Pmode, part1, part2));
 	}
       else
-	emit_insn (gen_tls_low (Pmode, a0, high, loc));
+	{
+	  /* Split tls symbol to high and low.  */
+	  rtx high = gen_rtx_HIGH (Pmode, copy_rtx (loc));
+
+	  high = loongarch_force_temporary (tmp, high);
+	  emit_insn (gen_tls_low (Pmode, a0, high, loc));
+	}
     }
   else
     emit_insn (loongarch_load_tls (a0, loc, type));
@@ -2870,20 +2872,30 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0)
 	    {
 	      if (loongarch_explicit_relocs_p (SYMBOL_GOT_DISP))
 		{
-		  rtx tmp1 = gen_reg_rtx (Pmode);
-		  rtx high = gen_reg_rtx (Pmode);
+		  gcc_assert (la_opt_explicit_relocs !=
+			      EXPLICIT_RELOCS_NONE);
 
-		  loongarch_emit_move (high,
-				       gen_rtx_HIGH (Pmode, loongarch_tls_symbol));
-		  loongarch_emit_move (tmp1, gen_rtx_LO_SUM (Pmode,
-							     gen_rtx_REG (Pmode, 0),
-							     loongarch_tls_symbol));
-		  emit_insn (gen_lui_h_lo20 (tmp1, tmp1, loongarch_tls_symbol));
-		  emit_insn (gen_lui_h_hi12 (tmp1, tmp1, loongarch_tls_symbol));
-		  loongarch_emit_move (dest,
-				       gen_rtx_MEM (Pmode,
-						    gen_rtx_PLUS (Pmode,
-								  high, tmp1)));
+		  rtx part1 = gen_reg_rtx (Pmode);
+		  rtx part2 = gen_reg_rtx (Pmode);
+
+		  emit_insn (
+		    gen_la_pcrel64_two_parts (part1, part2,
+					      loongarch_tls_symbol));
+		  loongarch_emit_move (
+		    dest,
+		    gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode,
+						      part1,
+						      part2)));
+
+		  /* Put an REG_EQUAL note here to allow CSE (storing
+		     part1 + part2, i.e. the address of tls_get_addr into
+		     a saved register and use it for multiple TLS
+		     accesses).  */
+		  rtx sum = gen_rtx_UNSPEC (
+		    Pmode, gen_rtvec (1, loongarch_tls_symbol),
+		    UNSPEC_ADDRESS_FIRST
+		    + loongarch_classify_symbol (loongarch_tls_symbol));
+		  set_unique_reg_note (get_last_insn (), REG_EQUAL, sum);
 		}
 	      else
 	       emit_insn (gen_movdi_symbolic_off64 (dest, loongarch_tls_symbol,
@@ -2946,24 +2958,30 @@ loongarch_legitimize_tls_address (rtx loc)
 	  dest = gen_reg_rtx (Pmode);
 	  if (loongarch_explicit_relocs_p (SYMBOL_TLS_IE))
 	    {
-	      tmp3 = gen_reg_rtx (Pmode);
-	      rtx high = gen_rtx_HIGH (Pmode, copy_rtx (tmp2));
-	      high = loongarch_force_temporary (tmp3, high);
-
 	      if (TARGET_CMODEL_EXTREME)
 		{
-		  rtx tmp3 = gen_reg_rtx (Pmode);
-		  emit_insn (gen_tls_low (Pmode, tmp3,
-					  gen_rtx_REG (Pmode, 0), tmp2));
-		  emit_insn (gen_lui_h_lo20 (tmp3, tmp3, tmp2));
-		  emit_insn (gen_lui_h_hi12 (tmp3, tmp3, tmp2));
+		  gcc_assert (la_opt_explicit_relocs
+			      != EXPLICIT_RELOCS_NONE);
+
+		  rtx part1 = gen_reg_rtx (Pmode);
+		  rtx part2 = gen_reg_rtx (Pmode);
+
+		  emit_insn (gen_la_pcrel64_two_parts (part1, part2,
+						       tmp2));
 		  emit_move_insn (tmp1,
 				  gen_rtx_MEM (Pmode,
 					       gen_rtx_PLUS (Pmode,
-							     high, tmp3)));
+							     part1,
+							     part2)));
 		}
 	      else
-		emit_insn (gen_ld_from_got (Pmode, tmp1, high, tmp2));
+		{
+		  tmp3 = gen_reg_rtx (Pmode);
+		  rtx high = gen_rtx_HIGH (Pmode, copy_rtx (tmp2));
+
+		  high = loongarch_force_temporary (tmp3, high);
+		  emit_insn (gen_ld_from_got (Pmode, tmp1, high, tmp2));
+		}
 	    }
 	  else
 	    emit_insn (loongarch_load_tls (tmp1, tmp2, SYMBOL_TLS_IE));
@@ -3142,24 +3160,23 @@ loongarch_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out)
       || !loongarch_split_symbol_type (symbol_type))
     return false;
 
-  rtx high, temp1 = NULL;
+  rtx high;
 
   if (temp == NULL)
     temp = gen_reg_rtx (Pmode);
 
-  /* Get the 12-31 bits of the address.  */
-  high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
-  high = loongarch_force_temporary (temp, high);
-
   if (loongarch_symbol_extreme_p (symbol_type) && can_create_pseudo_p ())
     {
       gcc_assert (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE);
 
-      temp1 = gen_reg_rtx (Pmode);
-      emit_move_insn (temp1, gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, 0),
-					     addr));
-      emit_insn (gen_lui_h_lo20 (temp1, temp1, addr));
-      emit_insn (gen_lui_h_hi12 (temp1, temp1, addr));
+      high = gen_reg_rtx (Pmode);
+      emit_insn (gen_la_pcrel64_two_parts (high, temp, addr));
+    }
+  else
+    {
+      /* Get the 12-31 bits of the address.  */
+      high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
+      high = loongarch_force_temporary (temp, high);
     }
 
   if (low_out)
@@ -3168,7 +3185,7 @@ loongarch_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out)
       case SYMBOL_PCREL64:
 	if (can_create_pseudo_p ())
 	  {
-	    *low_out = gen_rtx_PLUS (Pmode, high, temp1);
+	    *low_out = gen_rtx_PLUS (Pmode, high, temp);
 	    break;
 	  }
 	/* fall through */
@@ -3180,7 +3197,8 @@ loongarch_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out)
 	/* SYMBOL_GOT_DISP symbols are loaded from the GOT.  */
 	{
 	  if (TARGET_CMODEL_EXTREME && can_create_pseudo_p ())
-	    *low_out = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, high, temp1));
+	    *low_out = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, high,
+							 temp));
 	  else
 	    {
 	      rtx low = gen_rtx_LO_SUM (Pmode, high, addr);
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index 5a2b181716a..f27a263848d 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -84,6 +84,8 @@ (define_c_enum "unspec" [
   UNSPEC_CALL_VALUE_MULTIPLE_INTERNAL_1
 
   UNSPEC_LOAD_SYMBOL_OFFSET64
+  UNSPEC_LA_PCREL_64_PART1
+  UNSPEC_LA_PCREL_64_PART2
 ])
 
 (define_c_enum "unspecv" [
@@ -2224,6 +2226,24 @@ (define_insn_and_split "movdi_symbolic_off64"
  [(set_attr "mode" "DI")
   (set_attr "length" "5")])
 
+;; The 64-bit PC-relative part of address loading.
+;; Note that the psABI does not allow splitting it.
+(define_insn "la_pcrel64_two_parts"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(unspec:DI [(match_operand:DI 2 "") (pc)] UNSPEC_LA_PCREL_64_PART1))
+   (set (match_operand:DI 1 "register_operand" "=r")
+	(unspec:DI [(match_dup 2) (pc)] UNSPEC_LA_PCREL_64_PART2))]
+  "TARGET_ABI_LP64 && la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE"
+  {
+    return "pcalau12i\t%0,%r2\n\t"
+	   "addi.d\t%1,$r0,%L2\n\t"
+	   "lu32i.d\t%1,%R2\n\t"
+	   "lu52i.d\t%1,%1,%H2";
+  }
+  [(set_attr "move_type" "move")
+   (set_attr "mode" "DI")
+   (set_attr "length" "16")])
+
 ;; 32-bit Integer moves
 
 (define_expand "movsi"
diff --git a/gcc/testsuite/gcc.target/loongarch/cmodel-extreme-1.c b/gcc/testsuite/gcc.target/loongarch/cmodel-extreme-1.c
new file mode 100644
index 00000000000..564ee4017f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/cmodel-extreme-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O2 -mcmodel=extreme -fno-plt -mexplicit-relocs=always -fdump-rtl-final" } */
+
+int a;
+extern int b;
+__thread int c __attribute__ ((tls_model ("local-exec")));
+__thread int d __attribute__ ((tls_model ("initial-exec")));
+__thread int e __attribute__ ((tls_model ("local-dynamic")));
+__thread int f __attribute__ ((tls_model ("global-dynamic")));
+
+void
+test (void)
+{
+  a = b + c + d + e + f;
+}
+
+/* a, b, d, e, f, and __tls_get_addr.  */
+/* { dg-final { scan-rtl-dump-times "la_pcrel64_two_parts" 6 "final" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/cmodel-extreme-2.c b/gcc/testsuite/gcc.target/loongarch/cmodel-extreme-2.c
new file mode 100644
index 00000000000..ce834805f38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/cmodel-extreme-2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O2 -mcmodel=extreme -fno-plt -mexplicit-relocs=auto -fdump-rtl-final" } */
+
+#include "cmodel-extreme-1.c"
+
+/* a, b, d, e, f, and __tls_get_addr.  */
+/* { dg-final { scan-rtl-dump-times "la_pcrel64_two_parts" 6 "final" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c
index db1e0f85396..fdb4cf1ff7f 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c
@@ -1,31 +1,33 @@
 /* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */
+/* { dg-options "-mabi=lp64d -O2 -fno-pic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */
 /* { dg-final { scan-assembler "test:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */
 /* { dg-final { scan-assembler "test1:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */
 /* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */
 
+#define NOIPA __attribute__ ((noipa))
+
 extern void g (void);
-void
+NOIPA void
 f (void)
 {}
 
-static void
+NOIPA static void
 l (void)
 {}
 
-void
+NOIPA void
 test (void)
 {
   g ();
 }
 
-void
+NOIPA void
 test1 (void)
 {
   f ();
 }
 
-void
+NOIPA void
 test2 (void)
 {
   l ();
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c
index 21bf81ae837..dfba3882b97 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c
@@ -1,32 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */
+/* { dg-options "-mabi=lp64d -O2 -fpic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */
 /* { dg-final { scan-assembler "test:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */
 /* { dg-final { scan-assembler "test1:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */
 /* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */
 
-extern void g (void);
-void
-f (void)
-{}
-
-static void
-l (void)
-{}
-
-void
-test (void)
-{
-  g ();
-}
-
-void
-test1 (void)
-{
-  f ();
-}
-
-void
-test2 (void)
-{
-  l ();
-}
+#include "func-call-extreme-1.c"
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-3.c b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-3.c
index a4da44b4a3d..1f5234f83d1 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-3.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs=auto -mcmodel=extreme" } */
+/* { dg-options "-mabi=lp64d -O2 -fno-pic -fno-plt -mexplicit-relocs=auto -mcmodel=extreme" } */
 /* { dg-final { scan-assembler "test:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */
 /* { dg-final { scan-assembler "test1:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */
 /* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-4.c b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-4.c
index 16b00f4c5f2..c4228500635 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-4.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs=auto -mcmodel=extreme" } */
+/* { dg-options "-mabi=lp64d -O2 -fpic -fno-plt -mexplicit-relocs=auto -mcmodel=extreme" } */
 /* { dg-final { scan-assembler "test:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */
 /* { dg-final { scan-assembler "test1:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */
 /* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */
-- 
2.43.0

Re: [PATCH v4 0/4] When cmodel=extreme, add macro support and only support macros.

[chenglulu]

在 2024/1/26 下午4:49, Xi Ruoyao 写道:
> On Fri, 2024-01-26 at 15:37 +0800, Lulu Cheng wrote:
>> v3 -> v4:
>>    1. Add macro support for TLS symbols
>>    2. Added support for loading __get_tls_addr symbol address using call36.
>>    3. Merge template got_load_tls_{ld/gd/le/ie}.
>>    4. Enable explicit reloc for extreme TLS GD/LD with -mexplicit-relocs=auto.
> I've rebased and attached the patch to fix the bad split in -mexplicit-
> relocs={always,auto} -mcmodel=extreme on top of this series.  I've not
> tested it seriously though (only tested the added and modified test
> cases).
>
OK, I'll test the spec for correctness.

Re: [PATCH v4 0/4] When cmodel=extreme, add macro support and only support macros.

[Xi Ruoyao]

On Fri, 2024-01-26 at 16:59 +0800, chenglulu wrote:
> 
> 在 2024/1/26 下午4:49, Xi Ruoyao 写道:
> > On Fri, 2024-01-26 at 15:37 +0800, Lulu Cheng wrote:
> > > v3 -> v4:
> > >    1. Add macro support for TLS symbols
> > >    2. Added support for loading __get_tls_addr symbol address using call36.
> > >    3. Merge template got_load_tls_{ld/gd/le/ie}.
> > >    4. Enable explicit reloc for extreme TLS GD/LD with -mexplicit-relocs=auto.
> > I've rebased and attached the patch to fix the bad split in -mexplicit-
> > relocs={always,auto} -mcmodel=extreme on top of this series.  I've not
> > tested it seriously though (only tested the added and modified test
> > cases).
> > 
> OK, I'll test the spec for correctness.

I suppose this still won't work yet because Binutils is not fully fixed.
GAS has been changed not to emit R_LARCH_RELAX for "la.tls.ie a0, t0,
foo", but ld is still not checking if an R_LARCH_RELAX is after
R_LARCH_TLS_IE_PC_{HI20,LO12} properly.  Thus an invalid "partial" TLS
transition can still happen.

-- 
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University

Re: [PATCH v4 0/4] When cmodel=extreme, add macro support and only support macros.

[chenglulu]

在 2024/1/26 下午6:57, Xi Ruoyao 写道:
> On Fri, 2024-01-26 at 16:59 +0800, chenglulu wrote:
>> 在 2024/1/26 下午4:49, Xi Ruoyao 写道:
>>> On Fri, 2024-01-26 at 15:37 +0800, Lulu Cheng wrote:
>>>> v3 -> v4:
>>>>     1. Add macro support for TLS symbols
>>>>     2. Added support for loading __get_tls_addr symbol address using call36.
>>>>     3. Merge template got_load_tls_{ld/gd/le/ie}.
>>>>     4. Enable explicit reloc for extreme TLS GD/LD with -mexplicit-relocs=auto.
>>> I've rebased and attached the patch to fix the bad split in -mexplicit-
>>> relocs={always,auto} -mcmodel=extreme on top of this series.  I've not
>>> tested it seriously though (only tested the added and modified test
>>> cases).
>>>
>> OK, I'll test the spec for correctness.
> I suppose this still won't work yet because Binutils is not fully fixed.
> GAS has been changed not to emit R_LARCH_RELAX for "la.tls.ie a0, t0,
> foo", but ld is still not checking if an R_LARCH_RELAX is after
> R_LARCH_TLS_IE_PC_{HI20,LO12} properly.  Thus an invalid "partial" TLS
> transition can still happen.
I temporarily changed my binutils to turn off this function.;-)

>

Re: [PATCH v4 0/4] When cmodel=extreme, add macro support and only support macros.

[chenglulu]

在 2024/1/26 下午6:57, Xi Ruoyao 写道:
> On Fri, 2024-01-26 at 16:59 +0800, chenglulu wrote:
>> 在 2024/1/26 下午4:49, Xi Ruoyao 写道:
>>> On Fri, 2024-01-26 at 15:37 +0800, Lulu Cheng wrote:
>>>> v3 -> v4:
>>>>     1. Add macro support for TLS symbols
>>>>     2. Added support for loading __get_tls_addr symbol address using call36.
>>>>     3. Merge template got_load_tls_{ld/gd/le/ie}.
>>>>     4. Enable explicit reloc for extreme TLS GD/LD with -mexplicit-relocs=auto.
>>> I've rebased and attached the patch to fix the bad split in -mexplicit-
>>> relocs={always,auto} -mcmodel=extreme on top of this series.  I've not
>>> tested it seriously though (only tested the added and modified test
>>> cases).
>>>
>> OK, I'll test the spec for correctness.
> I suppose this still won't work yet because Binutils is not fully fixed.
> GAS has been changed not to emit R_LARCH_RELAX for "la.tls.ie a0, t0,
> foo", but ld is still not checking if an R_LARCH_RELAX is after
> R_LARCH_TLS_IE_PC_{HI20,LO12} properly.  Thus an invalid "partial" TLS
> transition can still happen.
>

The following situations are not handled in the patch:

diff --git a/gcc/config/loongarch/loongarch.cc 
b/gcc/config/loongarch/loongarch.cc

index 3fab4b64453..6336a9f696f 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -7472,7 +7472,13 @@ loongarch_output_mi_thunk (FILE *file, tree 
thunk_fndecl ATTRIBUTE_UNUSED,
      {
        if (TARGET_CMODEL_EXTREME)
         {
-         emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
+         if (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE)
+           {
+             emit_insn (gen_la_pcrel64_two_parts (temp1, temp2, fnaddr));
+             emit_move_insn (temp1, gen_rtx_PLUS (Pmode, temp1, temp2));
+           }
+         else
+           emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
           insn = emit_call_insn (gen_sibcall_internal (temp1, const0_rtx));
         }
        else
@@ -7482,7 +7488,15 @@ loongarch_output_mi_thunk (FILE *file, tree 
thunk_fndecl ATTRIBUTE_UNUSED,
    else
      {
        if (TARGET_CMODEL_EXTREME)
-       emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
+       {
+         if (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE)
+           {
+             emit_insn (gen_la_pcrel64_two_parts (temp1, temp2, fnaddr));
+             emit_move_insn (temp1, gen_rtx_PLUS (Pmode, temp1, temp2));
+           }
+         else
+           emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
+       }
        else
         loongarch_emit_move (temp1, fnaddr);

Re: [PATCH v4 0/4] When cmodel=extreme, add macro support and only support macros.

[Xi Ruoyao]

On Sat, 2024-01-27 at 11:15 +0800, chenglulu wrote:
> 
> 在 2024/1/26 下午6:57, Xi Ruoyao 写道:
> > On Fri, 2024-01-26 at 16:59 +0800, chenglulu wrote:
> > > 在 2024/1/26 下午4:49, Xi Ruoyao 写道:
> > > > On Fri, 2024-01-26 at 15:37 +0800, Lulu Cheng wrote:
> > > > > v3 -> v4:
> > > > >     1. Add macro support for TLS symbols
> > > > >     2. Added support for loading __get_tls_addr symbol address using call36.
> > > > >     3. Merge template got_load_tls_{ld/gd/le/ie}.
> > > > >     4. Enable explicit reloc for extreme TLS GD/LD with -mexplicit-relocs=auto.
> > > > I've rebased and attached the patch to fix the bad split in -mexplicit-
> > > > relocs={always,auto} -mcmodel=extreme on top of this series.  I've not
> > > > tested it seriously though (only tested the added and modified test
> > > > cases).
> > > > 
> > > OK, I'll test the spec for correctness.
> > I suppose this still won't work yet because Binutils is not fully fixed.
> > GAS has been changed not to emit R_LARCH_RELAX for "la.tls.ie a0, t0,
> > foo", but ld is still not checking if an R_LARCH_RELAX is after
> > R_LARCH_TLS_IE_PC_{HI20,LO12} properly.  Thus an invalid "partial" TLS
> > transition can still happen.
> > 
> 
> The following situations are not handled in the patch:
> 
> diff --git a/gcc/config/loongarch/loongarch.cc 
> b/gcc/config/loongarch/loongarch.cc
> 
> index 3fab4b64453..6336a9f696f 100644
> --- a/gcc/config/loongarch/loongarch.cc
> +++ b/gcc/config/loongarch/loongarch.cc
> @@ -7472,7 +7472,13 @@ loongarch_output_mi_thunk (FILE *file, tree 
> thunk_fndecl ATTRIBUTE_UNUSED,
>       {
>         if (TARGET_CMODEL_EXTREME)
>          {
> -         emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
> +         if (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE)
> +           {
> +             emit_insn (gen_la_pcrel64_two_parts (temp1, temp2, fnaddr));
> +             emit_move_insn (temp1, gen_rtx_PLUS (Pmode, temp1, temp2));
> +           }
> +         else
> +           emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
>            insn = emit_call_insn (gen_sibcall_internal (temp1, const0_rtx));
>          }
>         else
> @@ -7482,7 +7488,15 @@ loongarch_output_mi_thunk (FILE *file, tree 
> thunk_fndecl ATTRIBUTE_UNUSED,
>     else
>       {
>         if (TARGET_CMODEL_EXTREME)
> -       emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
> +       {
> +         if (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE)
> +           {
> +             emit_insn (gen_la_pcrel64_two_parts (temp1, temp2, fnaddr));
> +             emit_move_insn (temp1, gen_rtx_PLUS (Pmode, temp1, temp2));
> +           }
> +         else
> +           emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
> +       }
>         else
>          loongarch_emit_move (temp1, fnaddr);

In deed.  Considering the similarity of these two hunks I'll separate
the logic into a static function though.  And I'll also add some test
case for them...

-- 
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University

Re: [PATCH v4 0/4] When cmodel=extreme, add macro support and only support macros.

[Xi Ruoyao]

[-- Attachment #1: Type: text/plain, Size: 4940 bytes --]

On Sat, 2024-01-27 at 18:02 +0800, Xi Ruoyao wrote:
> On Sat, 2024-01-27 at 11:15 +0800, chenglulu wrote:
> > 
> > 在 2024/1/26 下午6:57, Xi Ruoyao 写道:
> > > On Fri, 2024-01-26 at 16:59 +0800, chenglulu wrote:
> > > > 在 2024/1/26 下午4:49, Xi Ruoyao 写道:
> > > > > On Fri, 2024-01-26 at 15:37 +0800, Lulu Cheng wrote:
> > > > > > v3 -> v4:
> > > > > >     1. Add macro support for TLS symbols
> > > > > >     2. Added support for loading __get_tls_addr symbol address using call36.
> > > > > >     3. Merge template got_load_tls_{ld/gd/le/ie}.
> > > > > >     4. Enable explicit reloc for extreme TLS GD/LD with -mexplicit-relocs=auto.
> > > > > I've rebased and attached the patch to fix the bad split in -mexplicit-
> > > > > relocs={always,auto} -mcmodel=extreme on top of this series.  I've not
> > > > > tested it seriously though (only tested the added and modified test
> > > > > cases).
> > > > > 
> > > > OK, I'll test the spec for correctness.
> > > I suppose this still won't work yet because Binutils is not fully fixed.
> > > GAS has been changed not to emit R_LARCH_RELAX for "la.tls.ie a0, t0,
> > > foo", but ld is still not checking if an R_LARCH_RELAX is after
> > > R_LARCH_TLS_IE_PC_{HI20,LO12} properly.  Thus an invalid "partial" TLS
> > > transition can still happen.
> > > 
> > 
> > The following situations are not handled in the patch:
> > 
> > diff --git a/gcc/config/loongarch/loongarch.cc 
> > b/gcc/config/loongarch/loongarch.cc
> > 
> > index 3fab4b64453..6336a9f696f 100644
> > --- a/gcc/config/loongarch/loongarch.cc
> > +++ b/gcc/config/loongarch/loongarch.cc
> > @@ -7472,7 +7472,13 @@ loongarch_output_mi_thunk (FILE *file, tree 
> > thunk_fndecl ATTRIBUTE_UNUSED,
> >       {
> >         if (TARGET_CMODEL_EXTREME)
> >          {
> > -         emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
> > +         if (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE)
> > +           {
> > +             emit_insn (gen_la_pcrel64_two_parts (temp1, temp2, fnaddr));
> > +             emit_move_insn (temp1, gen_rtx_PLUS (Pmode, temp1, temp2));
> > +           }
> > +         else
> > +           emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));

It looks like this part is unreachable: with -mcmodel=extreme
use_sibcall_p will never be true.

So cleaned up this part and fixed an ERROR in the added test:

diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index 3a97ba61362..7b8c85a1606 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -7481,21 +7481,24 @@ loongarch_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
      allowed, otherwise load the address into a register first.  */
   if (use_sibcall_p)
     {
-      if (TARGET_CMODEL_EXTREME)
-	{
-	  emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
-	  insn = emit_call_insn (gen_sibcall_internal (temp1, const0_rtx));
-	}
-      else
-	insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
+      /* If TARGET_CMODEL_EXTREME, we cannot do a direct jump at all
+	 and const_call_insn_operand should have returned false.  */
+      gcc_assert (!TARGET_CMODEL_EXTREME);
+
+      insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
       SIBLING_CALL_P (insn) = 1;
     }
   else
     {
-      if (TARGET_CMODEL_EXTREME)
+      if (!TARGET_CMODEL_EXTREME)
+	loongarch_emit_move (temp1, fnaddr);
+      else if (la_opt_explicit_relocs == EXPLICIT_RELOCS_NONE)
 	emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
       else
-	loongarch_emit_move (temp1, fnaddr);
+	{
+	  emit_insn (gen_la_pcrel64_two_parts (temp1, temp2, fnaddr));
+	  emit_move_insn (temp1, gen_rtx_PLUS (Pmode, temp1, temp2));
+	}
 
       emit_jump_insn (gen_indirect_jump (temp1));
     }
diff --git a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c
index 27baf4886d6..35bd4570a9e 100644
--- a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c
+++ b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -fPIC -mexplicit-relocs=auto -mcmodel=extreme -fno-plt" } */
-/* { dg-final { scan-assembler-not "la.tls.[lg]d" { target tls_native } } } */
+/* { dg-final { scan-assembler-not "la.tls.\[lg\]d" { target tls_native } } } */
 
 #include "./explicit-relocs-auto-tls-ld-gd.c"

And added 3 tests for output_mi_thunk.  The updated patch attached, now
running regression test.

-- 
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University

[-- Attachment #2: 0001-LoongArch-Don-t-split-the-instructions-containing-re.patch --]
[-- Type: text/x-patch, Size: 21428 bytes --]

From ecbadf341234fcec2e0c16e6b2435d117bf80446 Mon Sep 17 00:00:00 2001
From: Xi Ruoyao <xry111@xry111.site>
Date: Fri, 5 Jan 2024 18:40:06 +0800
Subject: [PATCH 5/4] LoongArch: Don't split the instructions containing relocs for
 extreme code model

The ABI mandates the pcalau12i/addi.d/lu32i.d/lu52i.d instructions for
addressing a symbol to be adjacent.  So model them as "one large
instruction", i.e. define_insn, with two output registers.  The real
address is the sum of these two registers.

The advantage of this approach is the RTL passes can still use ldx/stx
instructions to skip an addi.d instruction.

gcc/ChangeLog:

	* config/loongarch/loongarch.md (unspec): Add
	UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
	(la_pcrel64_two_parts): New define_insn.
	* config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
	typo in the comment.
	(loongarch_call_tls_get_addr): If -mcmodel=extreme
	-mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
	addressing the TLS symbol and __tls_get_addr.  Emit an REG_EQUAL
	note to allow CSE addressing __tls_get_addr.
	(loongarch_legitimize_tls_address): If -mcmodel=extreme
	-mexplicit-relocs={always,auto}, address TLS IE symbols with
	la_pcrel64_two_parts.
	(loongarch_split_symbol): If -mcmodel=extreme
	-mexplicit-relocs={always,auto}, address symbols with
	la_pcrel64_two_parts.
	(loongarch_output_mo_thunk): Clean up unreachable code.  If
	-mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
	thunks with la_pcrel64_two_parts.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/func-call-extreme-1.c (dg-options):
	Use -O2 instead of -O0 to ensure the pcalau12i/addi/lu32i/lu52i
	instruction sequences are not reordered by the compiler.
	(NOIPA): Disallow interprocedural optimizations.
	* gcc.target/loongarch/func-call-extreme-2.c: Remove the content
	duplicated from func-call-extreme-1.c, include it instead.
	(dg-options): Likewise.
	* gcc.target/loongarch/func-call-extreme-3.c (dg-options):
	Likewise.
	* gcc.target/loongarch/func-call-extreme-4.c (dg-options):
	Likewise.
	* gcc.target/loongarch/cmodel-extreme-1.c: New test.
	* gcc.target/loongarch/cmodel-extreme-2.c: New test.
	* g++.target/loongarch/cmodel-extreme-mi-thunk-1.C: New test.
	* g++.target/loongarch/cmodel-extreme-mi-thunk-2.C: New test.
	* g++.target/loongarch/cmodel-extreme-mi-thunk-3.C: New test.
	* gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c:
	Escape [] to avoid an ERROR in DejaGNU.
---
 gcc/config/loongarch/loongarch.cc             | 133 ++++++++++--------
 gcc/config/loongarch/loongarch.md             |  20 +++
 .../loongarch/cmodel-extreme-mi-thunk-1.C     |  11 ++
 .../loongarch/cmodel-extreme-mi-thunk-2.C     |   6 +
 .../loongarch/cmodel-extreme-mi-thunk-3.C     |   6 +
 .../gcc.target/loongarch/cmodel-extreme-1.c   |  18 +++
 .../gcc.target/loongarch/cmodel-extreme-2.c   |   7 +
 .../explicit-relocs-extreme-auto-tls-ld-gd.c  |   2 +-
 .../loongarch/func-call-extreme-1.c           |  14 +-
 .../loongarch/func-call-extreme-2.c           |  29 +---
 .../loongarch/func-call-extreme-3.c           |   2 +-
 .../loongarch/func-call-extreme-4.c           |   2 +-
 12 files changed, 158 insertions(+), 92 deletions(-)
 create mode 100644 gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-1.C
 create mode 100644 gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-2.C
 create mode 100644 gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-3.C
 create mode 100644 gcc/testsuite/gcc.target/loongarch/cmodel-extreme-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/cmodel-extreme-2.c

diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index 481903147b8..fd222cbfc31 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -2737,7 +2737,7 @@ loongarch_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
   return plus_constant (Pmode, reg, offset);
 }
 
-/* The __tls_get_attr symbol.  */
+/* The __tls_get_addr symbol.  */
 static GTY (()) rtx loongarch_tls_symbol;
 
 /* Load an entry for a TLS access.  */
@@ -2777,20 +2777,22 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0)
 
   if (loongarch_explicit_relocs_p (type))
     {
-      /* Split tls symbol to high and low.  */
-      rtx high = gen_rtx_HIGH (Pmode, copy_rtx (loc));
-      high = loongarch_force_temporary (tmp, high);
-
       if (TARGET_CMODEL_EXTREME)
 	{
-	  rtx tmp1 = gen_reg_rtx (Pmode);
-	  emit_insn (gen_tls_low (Pmode, tmp1, gen_rtx_REG (Pmode, 0), loc));
-	  emit_insn (gen_lui_h_lo20 (tmp1, tmp1, loc));
-	  emit_insn (gen_lui_h_hi12 (tmp1, tmp1, loc));
-	  emit_move_insn (a0, gen_rtx_PLUS (Pmode, high, tmp1));
+	  rtx part1 = gen_reg_rtx (Pmode);
+	  rtx part2 = gen_reg_rtx (Pmode);
+
+	  emit_insn (gen_la_pcrel64_two_parts (part1, part2, loc));
+	  emit_move_insn (a0, gen_rtx_PLUS (Pmode, part1, part2));
 	}
       else
-	emit_insn (gen_tls_low (Pmode, a0, high, loc));
+	{
+	  /* Split tls symbol to high and low.  */
+	  rtx high = gen_rtx_HIGH (Pmode, copy_rtx (loc));
+
+	  high = loongarch_force_temporary (tmp, high);
+	  emit_insn (gen_tls_low (Pmode, a0, high, loc));
+	}
     }
   else
     emit_insn (loongarch_load_tls (a0, loc, type));
@@ -2870,20 +2872,30 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0)
 	    {
 	      if (loongarch_explicit_relocs_p (SYMBOL_GOT_DISP))
 		{
-		  rtx tmp1 = gen_reg_rtx (Pmode);
-		  rtx high = gen_reg_rtx (Pmode);
+		  gcc_assert (la_opt_explicit_relocs !=
+			      EXPLICIT_RELOCS_NONE);
 
-		  loongarch_emit_move (high,
-				       gen_rtx_HIGH (Pmode, loongarch_tls_symbol));
-		  loongarch_emit_move (tmp1, gen_rtx_LO_SUM (Pmode,
-							     gen_rtx_REG (Pmode, 0),
-							     loongarch_tls_symbol));
-		  emit_insn (gen_lui_h_lo20 (tmp1, tmp1, loongarch_tls_symbol));
-		  emit_insn (gen_lui_h_hi12 (tmp1, tmp1, loongarch_tls_symbol));
-		  loongarch_emit_move (dest,
-				       gen_rtx_MEM (Pmode,
-						    gen_rtx_PLUS (Pmode,
-								  high, tmp1)));
+		  rtx part1 = gen_reg_rtx (Pmode);
+		  rtx part2 = gen_reg_rtx (Pmode);
+
+		  emit_insn (
+		    gen_la_pcrel64_two_parts (part1, part2,
+					      loongarch_tls_symbol));
+		  loongarch_emit_move (
+		    dest,
+		    gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode,
+						      part1,
+						      part2)));
+
+		  /* Put an REG_EQUAL note here to allow CSE (storing
+		     part1 + part2, i.e. the address of tls_get_addr into
+		     a saved register and use it for multiple TLS
+		     accesses).  */
+		  rtx sum = gen_rtx_UNSPEC (
+		    Pmode, gen_rtvec (1, loongarch_tls_symbol),
+		    UNSPEC_ADDRESS_FIRST
+		    + loongarch_classify_symbol (loongarch_tls_symbol));
+		  set_unique_reg_note (get_last_insn (), REG_EQUAL, sum);
 		}
 	      else
 	       emit_insn (gen_movdi_symbolic_off64 (dest, loongarch_tls_symbol,
@@ -2946,24 +2958,30 @@ loongarch_legitimize_tls_address (rtx loc)
 	  dest = gen_reg_rtx (Pmode);
 	  if (loongarch_explicit_relocs_p (SYMBOL_TLS_IE))
 	    {
-	      tmp3 = gen_reg_rtx (Pmode);
-	      rtx high = gen_rtx_HIGH (Pmode, copy_rtx (tmp2));
-	      high = loongarch_force_temporary (tmp3, high);
-
 	      if (TARGET_CMODEL_EXTREME)
 		{
-		  rtx tmp3 = gen_reg_rtx (Pmode);
-		  emit_insn (gen_tls_low (Pmode, tmp3,
-					  gen_rtx_REG (Pmode, 0), tmp2));
-		  emit_insn (gen_lui_h_lo20 (tmp3, tmp3, tmp2));
-		  emit_insn (gen_lui_h_hi12 (tmp3, tmp3, tmp2));
+		  gcc_assert (la_opt_explicit_relocs
+			      != EXPLICIT_RELOCS_NONE);
+
+		  rtx part1 = gen_reg_rtx (Pmode);
+		  rtx part2 = gen_reg_rtx (Pmode);
+
+		  emit_insn (gen_la_pcrel64_two_parts (part1, part2,
+						       tmp2));
 		  emit_move_insn (tmp1,
 				  gen_rtx_MEM (Pmode,
 					       gen_rtx_PLUS (Pmode,
-							     high, tmp3)));
+							     part1,
+							     part2)));
 		}
 	      else
-		emit_insn (gen_ld_from_got (Pmode, tmp1, high, tmp2));
+		{
+		  tmp3 = gen_reg_rtx (Pmode);
+		  rtx high = gen_rtx_HIGH (Pmode, copy_rtx (tmp2));
+
+		  high = loongarch_force_temporary (tmp3, high);
+		  emit_insn (gen_ld_from_got (Pmode, tmp1, high, tmp2));
+		}
 	    }
 	  else
 	    emit_insn (loongarch_load_tls (tmp1, tmp2, SYMBOL_TLS_IE));
@@ -3142,24 +3160,23 @@ loongarch_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out)
       || !loongarch_split_symbol_type (symbol_type))
     return false;
 
-  rtx high, temp1 = NULL;
+  rtx high;
 
   if (temp == NULL)
     temp = gen_reg_rtx (Pmode);
 
-  /* Get the 12-31 bits of the address.  */
-  high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
-  high = loongarch_force_temporary (temp, high);
-
   if (loongarch_symbol_extreme_p (symbol_type) && can_create_pseudo_p ())
     {
       gcc_assert (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE);
 
-      temp1 = gen_reg_rtx (Pmode);
-      emit_move_insn (temp1, gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, 0),
-					     addr));
-      emit_insn (gen_lui_h_lo20 (temp1, temp1, addr));
-      emit_insn (gen_lui_h_hi12 (temp1, temp1, addr));
+      high = gen_reg_rtx (Pmode);
+      emit_insn (gen_la_pcrel64_two_parts (high, temp, addr));
+    }
+  else
+    {
+      /* Get the 12-31 bits of the address.  */
+      high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
+      high = loongarch_force_temporary (temp, high);
     }
 
   if (low_out)
@@ -3168,7 +3185,7 @@ loongarch_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out)
       case SYMBOL_PCREL64:
 	if (can_create_pseudo_p ())
 	  {
-	    *low_out = gen_rtx_PLUS (Pmode, high, temp1);
+	    *low_out = gen_rtx_PLUS (Pmode, high, temp);
 	    break;
 	  }
 	/* fall through */
@@ -3180,7 +3197,8 @@ loongarch_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out)
 	/* SYMBOL_GOT_DISP symbols are loaded from the GOT.  */
 	{
 	  if (TARGET_CMODEL_EXTREME && can_create_pseudo_p ())
-	    *low_out = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, high, temp1));
+	    *low_out = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, high,
+							 temp));
 	  else
 	    {
 	      rtx low = gen_rtx_LO_SUM (Pmode, high, addr);
@@ -7450,21 +7468,24 @@ loongarch_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
      allowed, otherwise load the address into a register first.  */
   if (use_sibcall_p)
     {
-      if (TARGET_CMODEL_EXTREME)
-	{
-	  emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
-	  insn = emit_call_insn (gen_sibcall_internal (temp1, const0_rtx));
-	}
-      else
-	insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
+      /* If TARGET_CMODEL_EXTREME, we cannot do a direct jump at all
+	 and const_call_insn_operand should have returned false.  */
+      gcc_assert (!TARGET_CMODEL_EXTREME);
+
+      insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
       SIBLING_CALL_P (insn) = 1;
     }
   else
     {
-      if (TARGET_CMODEL_EXTREME)
+      if (!TARGET_CMODEL_EXTREME)
+	loongarch_emit_move (temp1, fnaddr);
+      else if (la_opt_explicit_relocs == EXPLICIT_RELOCS_NONE)
 	emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
       else
-	loongarch_emit_move (temp1, fnaddr);
+	{
+	  emit_insn (gen_la_pcrel64_two_parts (temp1, temp2, fnaddr));
+	  emit_move_insn (temp1, gen_rtx_PLUS (Pmode, temp1, temp2));
+	}
 
       emit_jump_insn (gen_indirect_jump (temp1));
     }
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index 5a2b181716a..f27a263848d 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -84,6 +84,8 @@ (define_c_enum "unspec" [
   UNSPEC_CALL_VALUE_MULTIPLE_INTERNAL_1
 
   UNSPEC_LOAD_SYMBOL_OFFSET64
+  UNSPEC_LA_PCREL_64_PART1
+  UNSPEC_LA_PCREL_64_PART2
 ])
 
 (define_c_enum "unspecv" [
@@ -2224,6 +2226,24 @@ (define_insn_and_split "movdi_symbolic_off64"
  [(set_attr "mode" "DI")
   (set_attr "length" "5")])
 
+;; The 64-bit PC-relative part of address loading.
+;; Note that the psABI does not allow splitting it.
+(define_insn "la_pcrel64_two_parts"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(unspec:DI [(match_operand:DI 2 "") (pc)] UNSPEC_LA_PCREL_64_PART1))
+   (set (match_operand:DI 1 "register_operand" "=r")
+	(unspec:DI [(match_dup 2) (pc)] UNSPEC_LA_PCREL_64_PART2))]
+  "TARGET_ABI_LP64 && la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE"
+  {
+    return "pcalau12i\t%0,%r2\n\t"
+	   "addi.d\t%1,$r0,%L2\n\t"
+	   "lu32i.d\t%1,%R2\n\t"
+	   "lu52i.d\t%1,%1,%H2";
+  }
+  [(set_attr "move_type" "move")
+   (set_attr "mode" "DI")
+   (set_attr "length" "16")])
+
 ;; 32-bit Integer moves
 
 (define_expand "movsi"
diff --git a/gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-1.C b/gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-1.C
new file mode 100644
index 00000000000..ff1f7c165e2
--- /dev/null
+++ b/gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-1.C
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-inline -march=loongarch64 -mabi=lp64d -O2 -mcmodel=extreme -fno-plt -mexplicit-relocs=always -mdirect-extern-access" } */
+
+struct A {
+  virtual ~A();
+};
+
+struct B : virtual A {};
+void var() { B(); }
+
+/* { dg-final { scan-assembler "pcalau12i\t\[^\n\]*%pc_hi20\\(\\.LTHUNK0\\)\n\taddi\\.d\t\[^\n\]*%pc_lo12\\(\\\.LTHUNK0\\)\n\tlu32i\\.d\t\[^\n\]*%pc64_lo20\\(\\.LTHUNK0\\)\n\tlu52i\\.d\t\[^\n\]*%pc64_hi12\\(\\.LTHUNK0\\)" } } */
diff --git a/gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-2.C b/gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-2.C
new file mode 100644
index 00000000000..c9aa16b410d
--- /dev/null
+++ b/gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-2.C
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-inline -march=loongarch64 -mabi=lp64d -O2 -mcmodel=extreme -fno-plt -mexplicit-relocs=auto -mdirect-extern-access" } */
+
+#include "cmodel-extreme-mi-thunk-1.C"
+
+/* { dg-final { scan-assembler "pcalau12i\t\[^\n\]*%pc_hi20\\(\\.LTHUNK0\\)\n\taddi\\.d\t\[^\n\]*%pc_lo12\\(\\\.LTHUNK0\\)\n\tlu32i\\.d\t\[^\n\]*%pc64_lo20\\(\\.LTHUNK0\\)\n\tlu52i\\.d\t\[^\n\]*%pc64_hi12\\(\\.LTHUNK0\\)" } } */
diff --git a/gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-3.C b/gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-3.C
new file mode 100644
index 00000000000..afb86c8bdee
--- /dev/null
+++ b/gcc/testsuite/g++.target/loongarch/cmodel-extreme-mi-thunk-3.C
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fno-inline -march=loongarch64 -mabi=lp64d -O2 -mcmodel=extreme -fno-plt -mexplicit-relocs=none -mdirect-extern-access" } */
+
+#include "cmodel-extreme-mi-thunk-1.C"
+
+/* { dg-final { scan-assembler "la.local\t\[^\n\]*\\.LTHUNK0" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/cmodel-extreme-1.c b/gcc/testsuite/gcc.target/loongarch/cmodel-extreme-1.c
new file mode 100644
index 00000000000..564ee4017f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/cmodel-extreme-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O2 -mcmodel=extreme -fno-plt -mexplicit-relocs=always -fdump-rtl-final" } */
+
+int a;
+extern int b;
+__thread int c __attribute__ ((tls_model ("local-exec")));
+__thread int d __attribute__ ((tls_model ("initial-exec")));
+__thread int e __attribute__ ((tls_model ("local-dynamic")));
+__thread int f __attribute__ ((tls_model ("global-dynamic")));
+
+void
+test (void)
+{
+  a = b + c + d + e + f;
+}
+
+/* a, b, d, e, f, and __tls_get_addr.  */
+/* { dg-final { scan-rtl-dump-times "la_pcrel64_two_parts" 6 "final" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/cmodel-extreme-2.c b/gcc/testsuite/gcc.target/loongarch/cmodel-extreme-2.c
new file mode 100644
index 00000000000..ce834805f38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/cmodel-extreme-2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O2 -mcmodel=extreme -fno-plt -mexplicit-relocs=auto -fdump-rtl-final" } */
+
+#include "cmodel-extreme-1.c"
+
+/* a, b, d, e, f, and __tls_get_addr.  */
+/* { dg-final { scan-rtl-dump-times "la_pcrel64_two_parts" 6 "final" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c
index 27baf4886d6..35bd4570a9e 100644
--- a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c
+++ b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -fPIC -mexplicit-relocs=auto -mcmodel=extreme -fno-plt" } */
-/* { dg-final { scan-assembler-not "la.tls.[lg]d" { target tls_native } } } */
+/* { dg-final { scan-assembler-not "la.tls.\[lg\]d" { target tls_native } } } */
 
 #include "./explicit-relocs-auto-tls-ld-gd.c"
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c
index db1e0f85396..fdb4cf1ff7f 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c
@@ -1,31 +1,33 @@
 /* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */
+/* { dg-options "-mabi=lp64d -O2 -fno-pic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */
 /* { dg-final { scan-assembler "test:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */
 /* { dg-final { scan-assembler "test1:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */
 /* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */
 
+#define NOIPA __attribute__ ((noipa))
+
 extern void g (void);
-void
+NOIPA void
 f (void)
 {}
 
-static void
+NOIPA static void
 l (void)
 {}
 
-void
+NOIPA void
 test (void)
 {
   g ();
 }
 
-void
+NOIPA void
 test1 (void)
 {
   f ();
 }
 
-void
+NOIPA void
 test2 (void)
 {
   l ();
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c
index 21bf81ae837..dfba3882b97 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c
@@ -1,32 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */
+/* { dg-options "-mabi=lp64d -O2 -fpic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */
 /* { dg-final { scan-assembler "test:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */
 /* { dg-final { scan-assembler "test1:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */
 /* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */
 
-extern void g (void);
-void
-f (void)
-{}
-
-static void
-l (void)
-{}
-
-void
-test (void)
-{
-  g ();
-}
-
-void
-test1 (void)
-{
-  f ();
-}
-
-void
-test2 (void)
-{
-  l ();
-}
+#include "func-call-extreme-1.c"
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-3.c b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-3.c
index a4da44b4a3d..1f5234f83d1 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-3.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs=auto -mcmodel=extreme" } */
+/* { dg-options "-mabi=lp64d -O2 -fno-pic -fno-plt -mexplicit-relocs=auto -mcmodel=extreme" } */
 /* { dg-final { scan-assembler "test:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */
 /* { dg-final { scan-assembler "test1:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */
 /* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-4.c b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-4.c
index 16b00f4c5f2..c4228500635 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-4.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs=auto -mcmodel=extreme" } */
+/* { dg-options "-mabi=lp64d -O2 -fpic -fno-plt -mexplicit-relocs=auto -mcmodel=extreme" } */
 /* { dg-final { scan-assembler "test:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */
 /* { dg-final { scan-assembler "test1:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */
 /* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */
-- 
2.43.0

Re: [PATCH v4 0/4] When cmodel=extreme, add macro support and only support macros.

[chenglulu]

在 2024/1/27 下午7:11, Xi Ruoyao 写道:
> On Sat, 2024-01-27 at 18:02 +0800, Xi Ruoyao wrote:
>> On Sat, 2024-01-27 at 11:15 +0800, chenglulu wrote:
>>> 在 2024/1/26 下午6:57, Xi Ruoyao 写道:
>>>> On Fri, 2024-01-26 at 16:59 +0800, chenglulu wrote:
>>>>> 在 2024/1/26 下午4:49, Xi Ruoyao 写道:
>>>>>> On Fri, 2024-01-26 at 15:37 +0800, Lulu Cheng wrote:
>>>>>>> v3 -> v4:
>>>>>>>      1. Add macro support for TLS symbols
>>>>>>>      2. Added support for loading __get_tls_addr symbol address using call36.
>>>>>>>      3. Merge template got_load_tls_{ld/gd/le/ie}.
>>>>>>>      4. Enable explicit reloc for extreme TLS GD/LD with -mexplicit-relocs=auto.
>>>>>> I've rebased and attached the patch to fix the bad split in -mexplicit-
>>>>>> relocs={always,auto} -mcmodel=extreme on top of this series.  I've not
>>>>>> tested it seriously though (only tested the added and modified test
>>>>>> cases).
>>>>>>
>>>>> OK, I'll test the spec for correctness.
>>>> I suppose this still won't work yet because Binutils is not fully fixed.
>>>> GAS has been changed not to emit R_LARCH_RELAX for "la.tls.ie a0, t0,
>>>> foo", but ld is still not checking if an R_LARCH_RELAX is after
>>>> R_LARCH_TLS_IE_PC_{HI20,LO12} properly.  Thus an invalid "partial" TLS
>>>> transition can still happen.
>>>>
>>> The following situations are not handled in the patch:
>>>
>>> diff --git a/gcc/config/loongarch/loongarch.cc
>>> b/gcc/config/loongarch/loongarch.cc
>>>
>>> index 3fab4b64453..6336a9f696f 100644
>>> --- a/gcc/config/loongarch/loongarch.cc
>>> +++ b/gcc/config/loongarch/loongarch.cc
>>> @@ -7472,7 +7472,13 @@ loongarch_output_mi_thunk (FILE *file, tree
>>> thunk_fndecl ATTRIBUTE_UNUSED,
>>>        {
>>>          if (TARGET_CMODEL_EXTREME)
>>>           {
>>> -         emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
>>> +         if (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE)
>>> +           {
>>> +             emit_insn (gen_la_pcrel64_two_parts (temp1, temp2, fnaddr));
>>> +             emit_move_insn (temp1, gen_rtx_PLUS (Pmode, temp1, temp2));
>>> +           }
>>> +         else
>>> +           emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
> It looks like this part is unreachable: with -mcmodel=extreme
> use_sibcall_p will never be true.
>
> So cleaned up this part and fixed an ERROR in the added test:
>
> diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
> index 3a97ba61362..7b8c85a1606 100644
> --- a/gcc/config/loongarch/loongarch.cc
> +++ b/gcc/config/loongarch/loongarch.cc
> @@ -7481,21 +7481,24 @@ loongarch_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
>        allowed, otherwise load the address into a register first.  */
>     if (use_sibcall_p)
>       {
> -      if (TARGET_CMODEL_EXTREME)
> -	{
> -	  emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
> -	  insn = emit_call_insn (gen_sibcall_internal (temp1, const0_rtx));
> -	}
> -      else
> -	insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
> +      /* If TARGET_CMODEL_EXTREME, we cannot do a direct jump at all
> +	 and const_call_insn_operand should have returned false.  */
> +      gcc_assert (!TARGET_CMODEL_EXTREME);
> +
> +      insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
>         SIBLING_CALL_P (insn) = 1;
>       }
>     else
>       {
> -      if (TARGET_CMODEL_EXTREME)
> +      if (!TARGET_CMODEL_EXTREME)
> +	loongarch_emit_move (temp1, fnaddr);
> +      else if (la_opt_explicit_relocs == EXPLICIT_RELOCS_NONE)
>   	emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
>         else
> -	loongarch_emit_move (temp1, fnaddr);
> +	{
> +	  emit_insn (gen_la_pcrel64_two_parts (temp1, temp2, fnaddr));
> +	  emit_move_insn (temp1, gen_rtx_PLUS (Pmode, temp1, temp2));
> +	}
>   
>         emit_jump_insn (gen_indirect_jump (temp1));
>       }
> diff --git a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c
> index 27baf4886d6..35bd4570a9e 100644
> --- a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c
> +++ b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c
> @@ -1,5 +1,5 @@
>   /* { dg-do compile } */
>   /* { dg-options "-O2 -fPIC -mexplicit-relocs=auto -mcmodel=extreme -fno-plt" } */
> -/* { dg-final { scan-assembler-not "la.tls.[lg]d" { target tls_native } } } */
> +/* { dg-final { scan-assembler-not "la.tls.\[lg\]d" { target tls_native } } } */
>   
>   #include "./explicit-relocs-auto-tls-ld-gd.c"
>
> And added 3 tests for output_mi_thunk.  The updated patch attached, now
> running regression test.
>

@@ -2870,20 +2872,30 @@ loongarch_call_tls_get_addr (rtx sym, enum 
loongarch_symbol_type type, rtx v0)
             {
               if (loongarch_explicit_relocs_p (SYMBOL_GOT_DISP))
                 {
-                 rtx tmp1 = gen_reg_rtx (Pmode);
-                 rtx high = gen_reg_rtx (Pmode);
+                 gcc_assert (la_opt_explicit_relocs !=
+ EXPLICIT_RELOCS_NONE);

This operator is written at the end of the line, and I think there is no 
problem with anything else.

But I need to see the results on Monday for the test.

Re: [PATCH v4 0/4] When cmodel=extreme, add macro support and only support macros.

[chenglulu]

在 2024/1/27 下午10:03, chenglulu 写道:
>
> 在 2024/1/27 下午7:11, Xi Ruoyao 写道:
>> On Sat, 2024-01-27 at 18:02 +0800, Xi Ruoyao wrote:
>>> On Sat, 2024-01-27 at 11:15 +0800, chenglulu wrote:
>>>> 在 2024/1/26 下午6:57, Xi Ruoyao 写道:
>>>>> On Fri, 2024-01-26 at 16:59 +0800, chenglulu wrote:
>>>>>> 在 2024/1/26 下午4:49, Xi Ruoyao 写道:
>>>>>>> On Fri, 2024-01-26 at 15:37 +0800, Lulu Cheng wrote:
>>>>>>>> v3 -> v4:
>>>>>>>>      1. Add macro support for TLS symbols
>>>>>>>>      2. Added support for loading __get_tls_addr symbol address 
>>>>>>>> using call36.
>>>>>>>>      3. Merge template got_load_tls_{ld/gd/le/ie}.
>>>>>>>>      4. Enable explicit reloc for extreme TLS GD/LD with 
>>>>>>>> -mexplicit-relocs=auto.
>>>>>>> I've rebased and attached the patch to fix the bad split in 
>>>>>>> -mexplicit-
>>>>>>> relocs={always,auto} -mcmodel=extreme on top of this series.  
>>>>>>> I've not
>>>>>>> tested it seriously though (only tested the added and modified test
>>>>>>> cases).
>>>>>>>
>>>>>> OK, I'll test the spec for correctness.
>>>>> I suppose this still won't work yet because Binutils is not fully 
>>>>> fixed.
>>>>> GAS has been changed not to emit R_LARCH_RELAX for "la.tls.ie a0, t0,
>>>>> foo", but ld is still not checking if an R_LARCH_RELAX is after
>>>>> R_LARCH_TLS_IE_PC_{HI20,LO12} properly.  Thus an invalid "partial" 
>>>>> TLS
>>>>> transition can still happen.
>>>>>
>>>> The following situations are not handled in the patch:
>>>>
>>>> diff --git a/gcc/config/loongarch/loongarch.cc
>>>> b/gcc/config/loongarch/loongarch.cc
>>>>
>>>> index 3fab4b64453..6336a9f696f 100644
>>>> --- a/gcc/config/loongarch/loongarch.cc
>>>> +++ b/gcc/config/loongarch/loongarch.cc
>>>> @@ -7472,7 +7472,13 @@ loongarch_output_mi_thunk (FILE *file, tree
>>>> thunk_fndecl ATTRIBUTE_UNUSED,
>>>>        {
>>>>          if (TARGET_CMODEL_EXTREME)
>>>>           {
>>>> -         emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
>>>> +         if (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE)
>>>> +           {
>>>> +             emit_insn (gen_la_pcrel64_two_parts (temp1, temp2, 
>>>> fnaddr));
>>>> +             emit_move_insn (temp1, gen_rtx_PLUS (Pmode, temp1, 
>>>> temp2));
>>>> +           }
>>>> +         else
>>>> +           emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, 
>>>> temp2));
>> It looks like this part is unreachable: with -mcmodel=extreme
>> use_sibcall_p will never be true.
>>
>> So cleaned up this part and fixed an ERROR in the added test:
>>
>> diff --git a/gcc/config/loongarch/loongarch.cc 
>> b/gcc/config/loongarch/loongarch.cc
>> index 3a97ba61362..7b8c85a1606 100644
>> --- a/gcc/config/loongarch/loongarch.cc
>> +++ b/gcc/config/loongarch/loongarch.cc
>> @@ -7481,21 +7481,24 @@ loongarch_output_mi_thunk (FILE *file, tree 
>> thunk_fndecl ATTRIBUTE_UNUSED,
>>        allowed, otherwise load the address into a register first.  */
>>     if (use_sibcall_p)
>>       {
>> -      if (TARGET_CMODEL_EXTREME)
>> -    {
>> -      emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
>> -      insn = emit_call_insn (gen_sibcall_internal (temp1, const0_rtx));
>> -    }
>> -      else
>> -    insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
>> +      /* If TARGET_CMODEL_EXTREME, we cannot do a direct jump at all
>> +     and const_call_insn_operand should have returned false. */
>> +      gcc_assert (!TARGET_CMODEL_EXTREME);
>> +
>> +      insn = emit_call_insn (gen_sibcall_internal (fnaddr, 
>> const0_rtx));
>>         SIBLING_CALL_P (insn) = 1;
>>       }
>>     else
>>       {
>> -      if (TARGET_CMODEL_EXTREME)
>> +      if (!TARGET_CMODEL_EXTREME)
>> +    loongarch_emit_move (temp1, fnaddr);
>> +      else if (la_opt_explicit_relocs == EXPLICIT_RELOCS_NONE)
>>       emit_insn (gen_movdi_symbolic_off64 (temp1, fnaddr, temp2));
>>         else
>> -    loongarch_emit_move (temp1, fnaddr);
>> +    {
>> +      emit_insn (gen_la_pcrel64_two_parts (temp1, temp2, fnaddr));
>> +      emit_move_insn (temp1, gen_rtx_PLUS (Pmode, temp1, temp2));
>> +    }
>>           emit_jump_insn (gen_indirect_jump (temp1));
>>       }
>> diff --git 
>> a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c 
>> b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c 
>>
>> index 27baf4886d6..35bd4570a9e 100644
>> --- 
>> a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c
>> +++ 
>> b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-extreme-auto-tls-ld-gd.c
>> @@ -1,5 +1,5 @@
>>   /* { dg-do compile } */
>>   /* { dg-options "-O2 -fPIC -mexplicit-relocs=auto -mcmodel=extreme 
>> -fno-plt" } */
>> -/* { dg-final { scan-assembler-not "la.tls.[lg]d" { target 
>> tls_native } } } */
>> +/* { dg-final { scan-assembler-not "la.tls.\[lg\]d" { target 
>> tls_native } } } */
>>     #include "./explicit-relocs-auto-tls-ld-gd.c"
>>
>> And added 3 tests for output_mi_thunk.  The updated patch attached, now
>> running regression test.
>>
>
> @@ -2870,20 +2872,30 @@ loongarch_call_tls_get_addr (rtx sym, enum 
> loongarch_symbol_type type, rtx v0)
>             {
>               if (loongarch_explicit_relocs_p (SYMBOL_GOT_DISP))
>                 {
> -                 rtx tmp1 = gen_reg_rtx (Pmode);
> -                 rtx high = gen_reg_rtx (Pmode);
> +                 gcc_assert (la_opt_explicit_relocs !=
> + EXPLICIT_RELOCS_NONE);
>
> This operator is written at the end of the line, and I think there is 
> no problem with anything else.
>
> But I need to see the results on Monday for the test.
>
>
The spec can pass the test, and I have no other problems.

Thanks!