From: YunQiang Su <yunqiang.su@cipunited.com>
To: "Maciej W. Rozycki" <macro@orcam.me.uk>,
Jeff Law <jeffreyalaw@gmail.com>
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU
Date: Tue, 15 Mar 2022 15:00:03 +0800 [thread overview]
Message-ID: <eb90fb37-26f1-4bf2-dd6c-94c2f49b814d@cipunited.com> (raw)
In-Reply-To: <alpine.DEB.2.21.2202120842330.34636@angie.orcam.me.uk>
在 2022/2/12 16:47, Maciej W. Rozycki 写道:
> On Fri, 11 Feb 2022, Jeff Law wrote:
>
>>> If MIPS MCU extension is enable, the IPL section in Cause register
>>> has been expand to 8bit instead of 6bit.
>>>
>>> gcc/ChangeLog:
>>>
>>> * config/mips/mips.cc (mips_expand_prologue):
>>> IPL is 8bit for MCU ASE.
>> OK
>
> But this is still wrong AFAICT.
>
Yes. you are right.
> The mask is applied to the CP0 Status register according to the comment,
> but the layout of the interrupt bit-field is different between the CP0
> Status and the CP0 Cause registers, so you can't just extract it from one
> of the two registers and directly apply to the other.
>
Since our case has 128 interrupts, so I didn't find this problem.
> I would like to know how this code has been verified.
And now new version sent with the test with 256 interrupts.
See v3 please.
>
> Maciej
> .
next prev parent reply other threads:[~2022-03-15 7:00 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-26 3:29 [PATCH] MIPS: use 8bit for IPL in Cause register YunQiang Su
2022-01-26 18:40 ` Maciej W. Rozycki
2022-02-09 3:18 ` [PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU YunQiang Su
2022-02-12 3:54 ` Jeff Law
2022-02-12 8:47 ` Maciej W. Rozycki
2022-03-15 7:00 ` YunQiang Su [this message]
2022-03-15 6:51 ` [PATCH v3] MIPS: IPL is 8bit in Cause and Status registers " YunQiang Su
2022-04-10 17:41 ` Maciej W. Rozycki
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