Re: [PATCH 1/1] RISC-V: fix stack access before allocation.

[Jeff Law <jeffreyalaw@gmail.com>]

On 11/27/22 22:28, Fei Gao wrote:
> In current riscv stack frame allocation, 2 steps are used. The first step allocates memories at least for callee saved GPRs and FPRs, and the second step allocates the rest if stack size is greater than signed 12-bit range. But it's observed in some cases, like gcc.target/riscv/stack_frame.c in my patch, callee saved FPRs fail to be included in the first step allocation, so we get generated instructions like this:
>
> 	li	t0,-16384
> 	addi	sp,sp,-48
> 	addi	t0,t0,752
> 	...
> 	fsw	fs4,-4(sp) #issue here of accessing before allocation
> 	...
> 	add	sp,sp,t0
>
> "fsw	fs4,-4(sp)" has issue here of accessing stack before allocation. Although "add	sp,sp,t0" reserves later the memory for fs4, it exposes a risk when an interrupt comes in between "fsw	fs4,-4(sp)" and "add	sp,sp,t0", resulting in a corruption in the stack storing fs4 after interrupt context saving and a failure to get the correct value of fs4 later.
>
> This patch fixes issue above, adapts testcases identified in regression tests, and add a new testcase for the change.
>
> gcc/ChangeLog:
>
>          * config/riscv/riscv.cc (riscv_first_stack_step):
>
> gcc/testsuite/ChangeLog:
>
>          * gcc.target/riscv/pr93304.c: Adapt testcase for the change, constrain match to assembly instructions only.
>          * gcc.target/riscv/rvv/base/spill-11.c: Adapt testcase for the change.
>          * gcc.target/riscv/stack_frame.c: New test.

They key here is that the MIN_FIRST_STEP wasn't including the FP save 
space.  The stack layout diagram before riscv_stack_align, combined with 
the info you provided made that pretty clear.


Good job tracking it down -- these can be tough to reproduce and thus 
tough to debug/fix.


I made minor adjustments to the ChangeLog and committed your change to 
the trunk.


Thanks,

Jeff