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From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Jeff Law <jeffreyalaw@gmail.com>,
	Kito Cheng <kito.cheng@gmail.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Andrew Waterman <andrew@sifive.com>,
	Jim Wilson <jim.wilson.gcc@gmail.com>
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH 1/1] RISC-V: Make "prefetch.i" built-in usable
Date: Tue, 29 Aug 2023 11:09:56 +0900	[thread overview]
Message-ID: <eba38e72-6adf-4b3f-aaeb-ddf794c75d8e@irq.a4lg.com> (raw)
In-Reply-To: <5b7219c9-76d6-574b-a7e4-2e0992a56198@gmail.com>

On 2023/08/29 6:20, Jeff Law wrote:
> 
> 
> On 8/9/23 21:10, Tsukasa OI via Gcc-patches wrote:
>> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>>
>> The "__builtin_riscv_zicbop_cbo_prefetchi" built-in function was terribly
>> broken so that practically unusable.  It emitted "prefetch.i" but with no
>> meaningful arguments.
>>
>> Though incompatible, this commit completely changes the function
>> prototype
>> of this built-in and makes it usable.  To minimize the functionality
>> issues,
>> it renames the built-in to "__builtin_riscv_zicbop_prefetch_i".
>>
>> gcc/ChangeLog:
>>
>>     * config/riscv/riscv-cmo.def: Fix function prototype.
>>     * config/riscv/riscv.md (riscv_prefetchi_<mode>): Fix instruction
>>     prototype.  Remove possible prefectch type argument
>>     * doc/extend.texi: Document __builtin_riscv_zicbop_prefetch_i.
>>
>> gcc/testsuite/ChangeLog:
>>
>>     * gcc.target/riscv/cmo-zicbop-1.c: Reflect new built-in prototype.
>>     * gcc.target/riscv/cmo-zicbop-2.c: Likewise.
>> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
>> index 688fd697255b..5658c7b7e113 100644
>> --- a/gcc/config/riscv/riscv.md
>> +++ b/gcc/config/riscv/riscv.md
>> @@ -3273,9 +3273,8 @@
>>   })
>>     (define_insn "riscv_prefetchi_<mode>"
>> -  [(unspec_volatile:X [(match_operand:X 0 "address_operand" "r")
>> -              (match_operand:X 1 "imm5_operand" "i")]
>> -              UNSPECV_PREI)]
>> +  [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
>> +    UNSPECV_PREI)]
>>     "TARGET_ZICBOP"
>>     "prefetch.i\t%a0"
>>   )
> What I would suggest is making a new predicate that accepts either a
> register or a register+offset where the offset fits in a signed 12 bit
> immediate.  Use that for operand 0's predicate and I think this will
> "just work" and cover all the cases supported by the prefetch.i
> instruction.
> 
> Jeff
> 

Seems reasonable.

If we have to break the compatibility anyway, adding an offset argument
is not a bad idea (though I think they will use inline assembly if a
non-zero offset is required).

I will try to add *optional* offset argument (with default value 0) like
 __builtin_speculation_safe_value built-in function in the next version.

Thanks,
Tsukasa

  reply	other threads:[~2023-08-29  2:09 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-10  3:10 [PATCH 0/1] " Tsukasa OI
2023-08-10  3:10 ` [PATCH 1/1] " Tsukasa OI
2023-08-28 21:20   ` Jeff Law
2023-08-29  2:09     ` Tsukasa OI [this message]
2023-08-29 13:47       ` Jeff Law

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