From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by sourceware.org (Postfix) with ESMTPS id 4D06D3858414 for ; Mon, 28 Nov 2022 16:44:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 4D06D3858414 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pj1-x102e.google.com with SMTP id w4-20020a17090ac98400b002186f5d7a4cso14621496pjt.0 for ; Mon, 28 Nov 2022 08:44:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=l5Bn6/IPcNSExdA10cvIN8JhEhyRsSa5x9Amk/4TqQY=; b=bjR+Jxb9BQjCQv19njzx3s5da2S5o05Vgs9udhxOycKoSFlyCa9QDlIU79l2HuQuEo zfgeASHlgO8IXW3e51Vay790CDuTM1ZGfKqySlU3xhWfDopN1E0J5pVDYAJSXmj1taKG ryrTXP/tSsFN9ZecC3FbC6MFLVlZ1uqS7vYVkfaSRvDh/IVXiz0tiDxR/n/vPv8aBVmm WLNneljtmQOYaMVlLki85oTJrF8SEb1EAMkQDmSqbEi1CHJKutmn28A3dKcoI/9beik9 NUEFJdWI6VVJz8aGla2XwJsFlIEHWu2DnWrSdLfQSIROE4afXV/zocNCx5XddvN8iwTz dN7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=l5Bn6/IPcNSExdA10cvIN8JhEhyRsSa5x9Amk/4TqQY=; b=5NuyyptzYNsoum9sdL6Cjs/nlwoPSXoaszG39a1cdSoVMz2hE7LWvEP/ISb/gH/pCX tntgjJh/62JE5b4NYegMgFPnCoyA9l4OVGwbjSACJta0dbE0cWvL6QBbe0ElYE2PiP9E FLrEEwoxUxxeHEG7ytmYyeG91MyBcqgVMts6pyKYpVDekwsBFnhkdD9blr8x3oVOAf6U Zkz+XCBvhstd3Qtt+PQ/egYUS3xCBfWQj0QmO+2+XGB653GlhQ8QXHL3lxS1MB6Br/Ao Xo3/h1i2WWQGWMScDpd/4tOxkGseDA0W8oAWAVHDz4nT9mEvAC8vC9U+n8b12/s0YZWi c4Xw== X-Gm-Message-State: ANoB5pmPOredd45ZXxfePx/YI1rJ5SfY6U1R7fyAqKeylmt2bdERNjJE TsM2IzzNaROM293hXmrurg8= X-Google-Smtp-Source: AA0mqf6j8iHfIgkTmWO4GRdJaauRB/siW6uE3etBIDJ0A7peuthcXWRY+H2pGwA0TcY45p56Ep28xw== X-Received: by 2002:a17:902:a605:b0:189:680e:c2e5 with SMTP id u5-20020a170902a60500b00189680ec2e5mr16947952plq.51.1669653858116; Mon, 28 Nov 2022 08:44:18 -0800 (PST) Received: from ?IPV6:2601:681:8600:13d0::f0a? ([2601:681:8600:13d0::f0a]) by smtp.gmail.com with ESMTPSA id t25-20020aa79479000000b00565cbad9616sm8271745pfq.6.2022.11.28.08.44.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Nov 2022 08:44:17 -0800 (PST) Message-ID: Date: Mon, 28 Nov 2022 09:44:16 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [PATCH] RISC-V: Add attributes for VSETVL PASS Content-Language: en-US To: juzhe.zhong@rivai.ai, gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com References: <20221128141406.242953-1-juzhe.zhong@rivai.ai> From: Jeff Law In-Reply-To: <20221128141406.242953-1-juzhe.zhong@rivai.ai> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 11/28/22 07:14, juzhe.zhong@rivai.ai wrote: > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config/riscv/riscv-protos.h (enum vlmul_type): New enum. > (get_vlmul): New function. > (get_ratio): Ditto. > * config/riscv/riscv-v.cc (struct mode_vtype_group): New struct. > (ENTRY): Adapt for attributes. > (enum vlmul_type): New enum. > (get_vlmul): New function. > (get_ratio): New function. > * config/riscv/riscv-vector-switch.def (ENTRY): Adapt for attributes. > * config/riscv/riscv.cc (ENTRY): Ditto. > * config/riscv/vector.md (false,true): Add attributes. I'm tempted to push this into the next stage1 given its arrival after stage1 close, but if the wider RISC-V maintainers want to see it move forward, I don't object strongly. I'm curious about the model you're using.  Is it going to be something similar to mode switching?  That's the first mental model that comes to mind.  Essentially we determine the VL needed for every chunk of code, then we do an LCM like algorithm to find the optimal placement points for VL sets to minimize the number of VL sets across all the paths through the CFG.  Never in a million years would I have expected we'd be considering reusing that code. Jeff