* [PATCH 2/4] rs6000: Rename 74 -> CR6_REGNO
2016-09-01 21:33 [PATCH 1/4] Hack: non-symbolic numeric constant warning Segher Boessenkool
2016-09-01 21:33 ` [PATCH 4/4] rs6000: Rename 110 -> VSCR_REGNO Segher Boessenkool
@ 2016-09-01 21:33 ` Segher Boessenkool
2016-09-01 21:33 ` [PATCH 3/4] rs6000: Rename 109 -> VRSAVE_REGNO Segher Boessenkool
2 siblings, 0 replies; 4+ messages in thread
From: Segher Boessenkool @ 2016-09-01 21:33 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
2016-09-01 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/altivec.md: Use CR6_REGNO instead of 74 throughout.
* config/rs6000/vector.md: Ditto.
* config/rs6000/vsx.md: Ditto.
---
gcc/config/rs6000/altivec.md | 30 +++++++++++++++---------------
gcc/config/rs6000/vector.md | 16 ++++++++--------
gcc/config/rs6000/vsx.md | 6 +++---
3 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 25472c29..480e64e 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -2274,7 +2274,7 @@ (define_insn "altivec_vupklpx"
;; Compare vectors producing a vector result and a predicate, setting CR6 to
;; indicate a combined status
(define_insn "*altivec_vcmpequ<VI_char>_p"
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC [(eq:CC (match_operand:VI2 1 "register_operand" "v")
(match_operand:VI2 2 "register_operand" "v"))]
UNSPEC_PREDICATE))
@@ -2286,7 +2286,7 @@ (define_insn "*altivec_vcmpequ<VI_char>_p"
[(set_attr "type" "veccmpfx")])
(define_insn "*altivec_vcmpgts<VI_char>_p"
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC [(gt:CC (match_operand:VI2 1 "register_operand" "v")
(match_operand:VI2 2 "register_operand" "v"))]
UNSPEC_PREDICATE))
@@ -2298,7 +2298,7 @@ (define_insn "*altivec_vcmpgts<VI_char>_p"
[(set_attr "type" "veccmpfx")])
(define_insn "*altivec_vcmpgtu<VI_char>_p"
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC [(gtu:CC (match_operand:VI2 1 "register_operand" "v")
(match_operand:VI2 2 "register_operand" "v"))]
UNSPEC_PREDICATE))
@@ -2310,7 +2310,7 @@ (define_insn "*altivec_vcmpgtu<VI_char>_p"
[(set_attr "type" "veccmpfx")])
(define_insn "*altivec_vcmpeqfp_p"
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC [(eq:CC (match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v"))]
UNSPEC_PREDICATE))
@@ -2322,7 +2322,7 @@ (define_insn "*altivec_vcmpeqfp_p"
[(set_attr "type" "veccmp")])
(define_insn "*altivec_vcmpgtfp_p"
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC [(gt:CC (match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v"))]
UNSPEC_PREDICATE))
@@ -2334,7 +2334,7 @@ (define_insn "*altivec_vcmpgtfp_p"
[(set_attr "type" "veccmp")])
(define_insn "*altivec_vcmpgefp_p"
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC [(ge:CC (match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v"))]
UNSPEC_PREDICATE))
@@ -2346,7 +2346,7 @@ (define_insn "*altivec_vcmpgefp_p"
[(set_attr "type" "veccmp")])
(define_insn "altivec_vcmpbfp_p"
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")]
UNSPEC_VCMPBFP))
@@ -3634,7 +3634,7 @@ (define_insn "bcd<bcd_add_sub>"
(match_operand:V1TI 2 "register_operand" "")
(match_operand:QI 3 "const_0_to_1_operand" "")]
UNSPEC_BCD_ADD_SUB))
- (clobber (reg:CCFP 74))]
+ (clobber (reg:CCFP CR6_REGNO))]
"TARGET_P8_VECTOR"
"bcd<bcd_add_sub>. %0,%1,%2,%3"
[(set_attr "length" "4")
@@ -3646,7 +3646,7 @@ (define_insn "bcd<bcd_add_sub>"
;; probably should be one that can go in the VMX (Altivec) registers, so we
;; can't use DDmode or DFmode.
(define_insn "*bcd<bcd_add_sub>_test"
- [(set (reg:CCFP 74)
+ [(set (reg:CCFP CR6_REGNO)
(compare:CCFP
(unspec:V2DF [(match_operand:V1TI 1 "register_operand" "v")
(match_operand:V1TI 2 "register_operand" "v")
@@ -3665,7 +3665,7 @@ (define_insn "*bcd<bcd_add_sub>_test2"
(match_operand:V1TI 2 "register_operand" "v")
(match_operand:QI 3 "const_0_to_1_operand" "i")]
UNSPEC_BCD_ADD_SUB))
- (set (reg:CCFP 74)
+ (set (reg:CCFP CR6_REGNO)
(compare:CCFP
(unspec:V2DF [(match_dup 1)
(match_dup 2)
@@ -3699,7 +3699,7 @@ (define_insn "darn"
[(set_attr "type" "integer")])
(define_expand "bcd<bcd_add_sub>_<code>"
- [(parallel [(set (reg:CCFP 74)
+ [(parallel [(set (reg:CCFP CR6_REGNO)
(compare:CCFP
(unspec:V2DF [(match_operand:V1TI 1 "register_operand" "")
(match_operand:V1TI 2 "register_operand" "")
@@ -3708,7 +3708,7 @@ (define_expand "bcd<bcd_add_sub>_<code>"
(match_dup 4)))
(clobber (match_scratch:V1TI 5 ""))])
(set (match_operand:SI 0 "register_operand" "")
- (BCD_TEST:SI (reg:CCFP 74)
+ (BCD_TEST:SI (reg:CCFP CR6_REGNO)
(const_int 0)))]
"TARGET_P8_VECTOR"
{
@@ -3727,8 +3727,8 @@ (define_peephole2
(match_operand:V1TI 2 "register_operand" "")
(match_operand:QI 3 "const_0_to_1_operand" "")]
UNSPEC_BCD_ADD_SUB))
- (clobber (reg:CCFP 74))])
- (parallel [(set (reg:CCFP 74)
+ (clobber (reg:CCFP CR6_REGNO))])
+ (parallel [(set (reg:CCFP CR6_REGNO)
(compare:CCFP
(unspec:V2DF [(match_dup 1)
(match_dup 2)
@@ -3742,7 +3742,7 @@ (define_peephole2
(match_dup 2)
(match_dup 3)]
UNSPEC_BCD_ADD_SUB))
- (set (reg:CCFP 74)
+ (set (reg:CCFP CR6_REGNO)
(compare:CCFP
(unspec:V2DF [(match_dup 1)
(match_dup 2)
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index fbfa9bf..d42de0f 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -670,7 +670,7 @@ (define_expand "vector_select_<mode>_uns"
;; setting CR6 to indicate a combined status
(define_expand "vector_eq_<mode>_p"
[(parallel
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand" "")
(match_operand:VEC_A 2 "vlogical_operand" ""))]
UNSPEC_PREDICATE))
@@ -682,7 +682,7 @@ (define_expand "vector_eq_<mode>_p"
(define_expand "vector_gt_<mode>_p"
[(parallel
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand" "")
(match_operand:VEC_A 2 "vlogical_operand" ""))]
UNSPEC_PREDICATE))
@@ -694,7 +694,7 @@ (define_expand "vector_gt_<mode>_p"
(define_expand "vector_ge_<mode>_p"
[(parallel
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" ""))]
UNSPEC_PREDICATE))
@@ -706,7 +706,7 @@ (define_expand "vector_ge_<mode>_p"
(define_expand "vector_gtu_<mode>_p"
[(parallel
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand" "")
(match_operand:VEC_I 2 "vint_operand" ""))]
UNSPEC_PREDICATE))
@@ -720,14 +720,14 @@ (define_expand "vector_gtu_<mode>_p"
(define_expand "cr6_test_for_zero"
[(set (match_operand:SI 0 "register_operand" "=r")
- (eq:SI (reg:CC 74)
+ (eq:SI (reg:CC CR6_REGNO)
(const_int 0)))]
"TARGET_ALTIVEC || TARGET_VSX"
"")
(define_expand "cr6_test_for_zero_reverse"
[(set (match_operand:SI 0 "register_operand" "=r")
- (eq:SI (reg:CC 74)
+ (eq:SI (reg:CC CR6_REGNO)
(const_int 0)))
(set (match_dup 0)
(xor:SI (match_dup 0)
@@ -737,14 +737,14 @@ (define_expand "cr6_test_for_zero_reverse"
(define_expand "cr6_test_for_lt"
[(set (match_operand:SI 0 "register_operand" "=r")
- (lt:SI (reg:CC 74)
+ (lt:SI (reg:CC CR6_REGNO)
(const_int 0)))]
"TARGET_ALTIVEC || TARGET_VSX"
"")
(define_expand "cr6_test_for_lt_reverse"
[(set (match_operand:SI 0 "register_operand" "=r")
- (lt:SI (reg:CC 74)
+ (lt:SI (reg:CC CR6_REGNO)
(const_int 0)))
(set (match_dup 0)
(xor:SI (match_dup 0)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 60917c5..359e424 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1499,7 +1499,7 @@ (define_insn "*vsx_ge<mode>"
;; Compare vectors producing a vector result and a predicate, setting CR6 to
;; indicate a combined status
(define_insn "*vsx_eq_<mode>_p"
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC
[(eq:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))]
@@ -1512,7 +1512,7 @@ (define_insn "*vsx_eq_<mode>_p"
[(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_gt_<mode>_p"
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC
[(gt:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))]
@@ -1525,7 +1525,7 @@ (define_insn "*vsx_gt_<mode>_p"
[(set_attr "type" "<VStype_simple>")])
(define_insn "*vsx_ge_<mode>_p"
- [(set (reg:CC 74)
+ [(set (reg:CC CR6_REGNO)
(unspec:CC
[(ge:CC (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,?<VSa>")
(match_operand:VSX_F 2 "vsx_register_operand" "<VSr>,?<VSa>"))]
--
1.9.3
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/4] Hack: non-symbolic numeric constant warning
@ 2016-09-01 21:33 Segher Boessenkool
2016-09-01 21:33 ` [PATCH 4/4] rs6000: Rename 110 -> VSCR_REGNO Segher Boessenkool
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Segher Boessenkool @ 2016-09-01 21:33 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
This patch prints a warning if a register number in the machine description
patterns is non-symbolic, to catch places that should use a constant from a
define_constants instead (e.g., LR_REGNO).
I hardcoded this to not warn for regno < 32, i.e. the GPRs on PowerPC.
That of course is not acceptable like this. If anyone wants to pick
this up and make that a target check, feel free :-) (The global variable
is not so hot either).
The next three patches in the series are what this patch uncovered; I'll
commit those to trunk.
Segher
---
gcc/read-md.c | 15 +++++++++++++++
gcc/read-md.h | 3 +++
gcc/read-rtl.c | 2 ++
3 files changed, 20 insertions(+)
diff --git a/gcc/read-md.c b/gcc/read-md.c
index b422d8d..7f5cdaf 100644
--- a/gcc/read-md.c
+++ b/gcc/read-md.c
@@ -94,6 +94,9 @@ static htab_t enum_types;
static void handle_file (directive_handler_t);
+/* For read_name: print a message if a number is non-symbolic. */
+int warn_if_non_symbolic_number;
+
/* Given an object that starts with a char * name field, return a hash
code for its name. */
@@ -450,6 +453,18 @@ read_name (struct md_name *name)
name->buffer[i] = 0;
name->string = name->buffer;
+ if (warn_if_non_symbolic_number)
+ {
+ const char *p = name->string;
+ while (*p && ISSPACE (*p))
+ p++;
+ if ((ISDIGIT (*p) || *p == '-' || *p == '+') && atoi (p) >= 32)
+ {
+ file_location loc (read_md_filename, read_md_lineno);
+ message_at (loc, "numeric constant %s is a plain number", p);
+ }
+ }
+
if (md_constants)
{
/* Do constant expansion. */
diff --git a/gcc/read-md.h b/gcc/read-md.h
index fa25951..6f9c34e 100644
--- a/gcc/read-md.h
+++ b/gcc/read-md.h
@@ -103,6 +103,9 @@ extern const char *read_md_filename;
extern struct obstack string_obstack;
extern void (*include_callback) (const char *);
+/* For read_name: print a message if a number is non-symbolic. */
+extern int warn_if_non_symbolic_number;
+
/* Read the next character from the MD file. */
static inline int
diff --git a/gcc/read-rtl.c b/gcc/read-rtl.c
index 4614e35..14e53cf 100644
--- a/gcc/read-rtl.c
+++ b/gcc/read-rtl.c
@@ -1311,7 +1311,9 @@ read_rtx_code (const char *code_name)
break;
case 'r':
+ warn_if_non_symbolic_number = 1;
read_name (&name);
+ warn_if_non_symbolic_number = 0;
validate_const_int (name.string);
set_regno_raw (return_rtx, atoi (name.string), 1);
REG_ATTRS (return_rtx) = NULL;
--
1.9.3
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 3/4] rs6000: Rename 109 -> VRSAVE_REGNO
2016-09-01 21:33 [PATCH 1/4] Hack: non-symbolic numeric constant warning Segher Boessenkool
2016-09-01 21:33 ` [PATCH 4/4] rs6000: Rename 110 -> VSCR_REGNO Segher Boessenkool
2016-09-01 21:33 ` [PATCH 2/4] rs6000: Rename 74 -> CR6_REGNO Segher Boessenkool
@ 2016-09-01 21:33 ` Segher Boessenkool
2 siblings, 0 replies; 4+ messages in thread
From: Segher Boessenkool @ 2016-09-01 21:33 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
2016-09-01 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/altivec.md: Use VRSAVE_REGNO instead of 109 throughout.
---
gcc/config/rs6000/altivec.md | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 480e64e..335c052 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -371,7 +371,7 @@ (define_split
(define_insn "get_vrsave_internal"
[(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(reg:SI 109)] UNSPEC_GET_VRSAVE))]
+ (unspec:SI [(reg:SI VRSAVE_REGNO)] UNSPEC_GET_VRSAVE))]
"TARGET_ALTIVEC"
{
if (TARGET_MACHO)
@@ -383,9 +383,9 @@ (define_insn "get_vrsave_internal"
(define_insn "*set_vrsave_internal"
[(match_parallel 0 "vrsave_operation"
- [(set (reg:SI 109)
+ [(set (reg:SI VRSAVE_REGNO)
(unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
- (reg:SI 109)] UNSPECV_SET_VRSAVE))])]
+ (reg:SI VRSAVE_REGNO)] UNSPECV_SET_VRSAVE))])]
"TARGET_ALTIVEC"
{
if (TARGET_MACHO)
--
1.9.3
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 4/4] rs6000: Rename 110 -> VSCR_REGNO
2016-09-01 21:33 [PATCH 1/4] Hack: non-symbolic numeric constant warning Segher Boessenkool
@ 2016-09-01 21:33 ` Segher Boessenkool
2016-09-01 21:33 ` [PATCH 2/4] rs6000: Rename 74 -> CR6_REGNO Segher Boessenkool
2016-09-01 21:33 ` [PATCH 3/4] rs6000: Rename 109 -> VRSAVE_REGNO Segher Boessenkool
2 siblings, 0 replies; 4+ messages in thread
From: Segher Boessenkool @ 2016-09-01 21:33 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
2016-09-01 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/altivec.md: Use VSCR_REGNO instead of 110 throughout.
---
gcc/config/rs6000/altivec.md | 37 +++++++++++++++++++------------------
1 file changed, 19 insertions(+), 18 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 335c052..857f257 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -508,7 +508,7 @@ (define_insn "altivec_vaddu<VI_char>s"
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
(match_operand:VI 2 "register_operand" "v")]
UNSPEC_VADDU))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"<VI_unit>"
"vaddu<VI_char>s %0,%1,%2"
[(set_attr "type" "vecsimple")])
@@ -518,7 +518,7 @@ (define_insn "altivec_vadds<VI_char>s"
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
(match_operand:VI 2 "register_operand" "v")]
UNSPEC_VADDS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
"vadds<VI_char>s %0,%1,%2"
[(set_attr "type" "vecsimple")])
@@ -554,7 +554,7 @@ (define_insn "altivec_vsubu<VI_char>s"
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
(match_operand:VI 2 "register_operand" "v")]
UNSPEC_VSUBU))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
"vsubu<VI_char>s %0,%1,%2"
[(set_attr "type" "vecsimple")])
@@ -564,7 +564,7 @@ (define_insn "altivec_vsubs<VI_char>s"
(unspec:VI [(match_operand:VI 1 "register_operand" "v")
(match_operand:VI 2 "register_operand" "v")]
UNSPEC_VSUBS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
"vsubs<VI_char>s %0,%1,%2"
[(set_attr "type" "vecsimple")])
@@ -830,7 +830,7 @@ (define_insn "altivec_vmsumuhs"
(match_operand:V8HI 2 "register_operand" "v")
(match_operand:V4SI 3 "register_operand" "v")]
UNSPEC_VMSUMUHS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"TARGET_ALTIVEC"
"vmsumuhs %0,%1,%2,%3"
[(set_attr "type" "veccomplex")])
@@ -841,7 +841,7 @@ (define_insn "altivec_vmsumshs"
(match_operand:V8HI 2 "register_operand" "v")
(match_operand:V4SI 3 "register_operand" "v")]
UNSPEC_VMSUMSHS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"TARGET_ALTIVEC"
"vmsumshs %0,%1,%2,%3"
[(set_attr "type" "veccomplex")])
@@ -902,7 +902,7 @@ (define_insn "altivec_vmhaddshs"
(match_operand:V8HI 2 "register_operand" "v")
(match_operand:V8HI 3 "register_operand" "v")]
UNSPEC_VMHADDSHS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"TARGET_ALTIVEC"
"vmhaddshs %0,%1,%2,%3"
[(set_attr "type" "veccomplex")])
@@ -913,7 +913,7 @@ (define_insn "altivec_vmhraddshs"
(match_operand:V8HI 2 "register_operand" "v")
(match_operand:V8HI 3 "register_operand" "v")]
UNSPEC_VMHRADDSHS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"TARGET_ALTIVEC"
"vmhraddshs %0,%1,%2,%3"
[(set_attr "type" "veccomplex")])
@@ -1699,7 +1699,7 @@ (define_insn "altivec_vsum4ubs"
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")]
UNSPEC_VSUM4UBS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"TARGET_ALTIVEC"
"vsum4ubs %0,%1,%2"
[(set_attr "type" "veccomplex")])
@@ -1709,7 +1709,7 @@ (define_insn "altivec_vsum4s<VI_char>s"
(unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")]
UNSPEC_VSUM4S))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"TARGET_ALTIVEC"
"vsum4s<VI_char>s %0,%1,%2"
[(set_attr "type" "veccomplex")])
@@ -1722,7 +1722,7 @@ (define_insn "altivec_vsum2sws"
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")]
UNSPEC_VSUM2SWS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))
(clobber (match_scratch:V4SI 3 "=v"))]
"TARGET_ALTIVEC"
{
@@ -1743,7 +1743,7 @@ (define_insn "altivec_vsumsws"
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")]
UNSPEC_VSUMSWS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))
(clobber (match_scratch:V4SI 3 "=v"))]
"TARGET_ALTIVEC"
{
@@ -1764,7 +1764,7 @@ (define_insn "altivec_vsumsws_direct"
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")]
UNSPEC_VSUMSWS_DIRECT))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"TARGET_ALTIVEC"
"vsumsws %0,%1,%2"
[(set_attr "type" "veccomplex")])
@@ -2124,7 +2124,7 @@ (define_insn "altivec_vctuxs"
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:QI 2 "immediate_operand" "i")]
UNSPEC_VCTUXS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"TARGET_ALTIVEC"
"vctuxs %0,%1,%2"
[(set_attr "type" "vecfloat")])
@@ -2134,7 +2134,7 @@ (define_insn "altivec_vctsxs"
(unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:QI 2 "immediate_operand" "i")]
UNSPEC_VCTSXS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
+ (set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
"TARGET_ALTIVEC"
"vctsxs %0,%1,%2"
[(set_attr "type" "vecfloat")])
@@ -2359,7 +2359,7 @@ (define_insn "altivec_vcmpbfp_p"
[(set_attr "type" "veccmp")])
(define_insn "altivec_mtvscr"
- [(set (reg:SI 110)
+ [(set (reg:SI VSCR_REGNO)
(unspec_volatile:SI
[(match_operand:V4SI 0 "register_operand" "v")] UNSPECV_MTVSCR))]
"TARGET_ALTIVEC"
@@ -2368,7 +2368,7 @@ (define_insn "altivec_mtvscr"
(define_insn "altivec_mfvscr"
[(set (match_operand:V8HI 0 "register_operand" "=v")
- (unspec_volatile:V8HI [(reg:SI 110)] UNSPECV_MFVSCR))]
+ (unspec_volatile:V8HI [(reg:SI VSCR_REGNO)] UNSPECV_MFVSCR))]
"TARGET_ALTIVEC"
"mfvscr %0"
[(set_attr "type" "vecsimple")])
@@ -2757,7 +2757,8 @@ (define_expand "altivec_abss_<mode>"
(unspec:VI [(match_dup 2)
(match_operand:VI 1 "register_operand" "v")]
UNSPEC_VSUBS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))])
+ (set (reg:SI VSCR_REGNO)
+ (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))])
(set (match_operand:VI 0 "register_operand" "=v")
(smax:VI (match_dup 1) (match_dup 3)))]
"TARGET_ALTIVEC"
--
1.9.3
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2016-09-01 21:33 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-09-01 21:33 [PATCH 1/4] Hack: non-symbolic numeric constant warning Segher Boessenkool
2016-09-01 21:33 ` [PATCH 4/4] rs6000: Rename 110 -> VSCR_REGNO Segher Boessenkool
2016-09-01 21:33 ` [PATCH 2/4] rs6000: Rename 74 -> CR6_REGNO Segher Boessenkool
2016-09-01 21:33 ` [PATCH 3/4] rs6000: Rename 109 -> VRSAVE_REGNO Segher Boessenkool
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