From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 24133 invoked by alias); 2 Oct 2018 22:28:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 24119 invoked by uid 89); 2 Oct 2018 22:28:03 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-12.1 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 spammy=excellent, fh, Hx-languages-length:1138 X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 02 Oct 2018 22:28:02 +0000 Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w92MOFcX136525 for ; Tue, 2 Oct 2018 18:28:00 -0400 Received: from e32.co.us.ibm.com (e32.co.us.ibm.com [32.97.110.150]) by mx0a-001b2d01.pphosted.com with ESMTP id 2mvfb8cjbs-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 02 Oct 2018 18:27:59 -0400 Received: from localhost by e32.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 2 Oct 2018 16:27:58 -0600 Received: from b03cxnp08027.gho.boulder.ibm.com (9.17.130.19) by e32.co.us.ibm.com (192.168.1.132) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 2 Oct 2018 16:27:55 -0600 Received: from b03ledav006.gho.boulder.ibm.com (b03ledav006.gho.boulder.ibm.com [9.17.130.237]) by b03cxnp08027.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w92MRskA46596348 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 2 Oct 2018 15:27:54 -0700 Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 724B5C605D; Tue, 2 Oct 2018 16:27:54 -0600 (MDT) Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B1A6FC6059; Tue, 2 Oct 2018 16:27:53 -0600 (MDT) Received: from otta.local (unknown [9.80.200.29]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP; Tue, 2 Oct 2018 16:27:53 -0600 (MDT) Subject: Re: [PATCH 0/2][IRA,LRA] Fix PR86939, IRA incorrectly creates an interference between a pseudo register and a hard register To: "H.J. Lu" Cc: GCC Patches , Vladimir Makarov , Jeffrey Law References: <616affd5-5140-8e15-9081-1635f7d4e700@redhat.com> <6ff45a7e-2415-2d18-1d53-5a50964a2174@linux.ibm.com> <31d4558f-11d0-67d4-b7e9-784243c0ab05@linux.ibm.com> From: Peter Bergner Date: Wed, 03 Oct 2018 00:35:00 -0000 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.13; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit x-cbid: 18100222-0004-0000-0000-0000149605FF X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00009811; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000267; SDB=6.01096978; UDB=6.00567272; IPR=6.00877021; MB=3.00023593; MTD=3.00000008; XFM=3.00000015; UTC=2018-10-02 22:27:56 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18100222-0005-0000-0000-00008904710B Message-Id: X-IsSubscribed: yes X-SW-Source: 2018-10/txt/msg00152.txt.bz2 On 10/2/18 4:52 PM, H.J. Lu wrote: > I saw the same failures: > > FAIL: gcc.target/i386/pr49095.c scan-assembler-times \\), % 8 > FAIL: gcc.target/i386/pr49095.c scan-assembler-times \\), % 8 > > I think the new ones are better, especially in 32-bit case: Excellent! Does the following test case patch make it so that it PASSes again? Peter Index: gcc/testsuite/gcc.target/i386/pr49095.c =================================================================== --- gcc/testsuite/gcc.target/i386/pr49095.c (revision 264793) +++ gcc/testsuite/gcc.target/i386/pr49095.c (working copy) @@ -73,4 +73,5 @@ G (long) /* { dg-final { scan-assembler-not "test\[lq\]" } } */ /* The {f,h}{char,short,int,long}xor functions aren't optimized into a RMW instruction, so need load, modify and store. FIXME eventually. */ -/* { dg-final { scan-assembler-times "\\), %" 8 } } */ +/* { dg-final { scan-assembler-times "\\), %" 57 { target { ia32 } } } } */ +/* { dg-final { scan-assembler-times "\\), %" 45 { target { lp64 } } } } */