From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dedi548.your-server.de (dedi548.your-server.de [85.10.215.148]) by sourceware.org (Postfix) with ESMTPS id B8E373858C54 for ; Fri, 28 Oct 2022 05:47:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B8E373858C54 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embedded-brains.de Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embedded-brains.de Received: from sslproxy03.your-server.de ([88.198.220.132]) by dedi548.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1ooIDC-0002hn-Q3; Fri, 28 Oct 2022 07:47:22 +0200 Received: from [82.100.198.138] (helo=mail.embedded-brains.de) by sslproxy03.your-server.de with esmtpsa (TLSv1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1ooIDC-000GmP-C0; Fri, 28 Oct 2022 07:47:22 +0200 Received: from localhost (localhost [127.0.0.1]) by mail.embedded-brains.de (Postfix) with ESMTP id 0EB77480179; Fri, 28 Oct 2022 07:47:22 +0200 (CEST) Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id axEcD3PTwZbU; Fri, 28 Oct 2022 07:47:21 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by mail.embedded-brains.de (Postfix) with ESMTP id 84E9C48019B; Fri, 28 Oct 2022 07:47:21 +0200 (CEST) X-Virus-Scanned: amavisd-new at zimbra.eb.localhost Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id TT0fFZvs0-Sl; Fri, 28 Oct 2022 07:47:21 +0200 (CEST) Received: from [10.10.171.6] (unknown [10.10.171.6]) by mail.embedded-brains.de (Postfix) with ESMTPSA id 3C15B480179; Fri, 28 Oct 2022 07:47:21 +0200 (CEST) Message-ID: Date: Fri, 28 Oct 2022 07:47:20 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH] riscv/RTEMS: Add RISCV_GCOV_TYPE_SIZE Content-Language: en-US To: Palmer Dabbelt , gcc-patches@gcc.gnu.org, Jeff Law References: From: Sebastian Huber In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-Authenticated-Sender: smtp-embedded@poldinet.de X-Virus-Scanned: Clear (ClamAV 0.103.7/26701/Thu Oct 27 09:54:47 2022) X-Spam-Status: No, score=-3.8 required=5.0 tests=BAYES_00,BODY_8BITS,KAM_DMARC_STATUS,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 28/10/2022 01:05, Palmer Dabbelt wrote: > On Thu, 27 Oct 2022 15:56:17 PDT (-0700), gcc-patches@gcc.gnu.org wrote= : >> >> On 10/26/22 01:49, Sebastian Huber wrote: >>> The RV32A extension does not support 64-bit atomic operations.=C2=A0 = For=20 >>> RTEMS, use >>> a 32-bit gcov type for RV32. >>> >>> gcc/ChangeLog: >>> >>> =C2=A0=C2=A0=C2=A0=C2=A0* config/riscv/riscv.cc (riscv_gcov_type_size= ): New. >>> =C2=A0=C2=A0=C2=A0=C2=A0(TARGET_GCOV_TYPE_SIZE): Likewise. >>> =C2=A0=C2=A0=C2=A0=C2=A0* config/riscv/rtems.h (RISCV_GCOV_TYPE_SIZE)= : New. >> >> Why make this specific to rtems?=C2=A0 ISTM the logic behind this chan= ge >> would apply independently of the os. Reducing the gcov type to 32-bit has the drawback that the program=20 runtime is reduced. I am not sure if this is generally acceptable. >=20 > Looks like rv32gc is just broken here: >=20 > $ cat test.s > int func(int x) { return x + 1; } > $ gcc -march=3Drv32gc -O3 -fprofile-update=3Datomic -fprofile-arcs test= .c -S=20 > -o- > func(int): > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 lui=C2=A0=C2=A0=C2=A0=C2=A0 a4,%h= i(__gcov0.func(int)) > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 lw=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 = a5,%lo(__gcov0.func(int))(a4) > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 lw=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 = a2,%lo(__gcov0.func(int)+4)(a4) > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 addi=C2=A0=C2=A0=C2=A0 a0,a0,1 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 addi=C2=A0=C2=A0=C2=A0 a3,a5,1 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sltu=C2=A0=C2=A0=C2=A0 a5,a3,a5 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 add=C2=A0=C2=A0=C2=A0=C2=A0 a5,a5= ,a2 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sw=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 = a3,%lo(__gcov0.func(int))(a4) > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sw=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 = a5,%lo(__gcov0.func(int)+4)(a4) > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ret > _sub_I_00100_0: > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 lui=C2=A0=C2=A0=C2=A0=C2=A0 a0,%h= i(.LANCHOR0) > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 addi=C2=A0=C2=A0=C2=A0 a0,a0,%lo(= .LANCHOR0) > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 tail=C2=A0=C2=A0=C2=A0 __gcov_ini= t > _sub_D_00100_1: > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 tail=C2=A0=C2=A0=C2=A0 __gcov_exi= t > __gcov0.func(int): > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .zero=C2=A0=C2=A0 8 >=20 > Those are not atomic... Well, you get at least a warning: test.c:1:1: warning: target does not support atomic profile update,=20 single mode is selected With the patch you get: riscv-rtems6-gcc -march=3Drv32gc -O3 -fprofile-update=3Datomic=20 -fprofile-arcs test.c -S -o- func: lui a5,%hi(__gcov0.func) li a4,1 addi a5,a5,%lo(__gcov0.func) amoadd.w zero,a4,0(a5) addi a0,a0,1 ret .size func, .-func The Armv7-A doesn't have an issue with 64-bit atomics: arm-rtems6-gcc -march=3Darmv7-a -O3 -fprofile-update=3Datomic -fprofile-a= rcs=20 test.c -S -o- func: @ args =3D 0, pretend =3D 0, frame =3D 0 @ frame_needed =3D 0, uses_anonymous_args =3D 0 @ link register save eliminated. movw r3, #:lower16:.LANCHOR0 movt r3, #:upper16:.LANCHOR0 push {r4, r5, r6, r7} mov r4, #1 mov r5, #0 .L2: ldrexd r6, r7, [r3] adds r6, r6, r4 adc r7, r7, r5 strexd r1, r6, r7, [r3] cmp r1, #0 bne .L2 add r0, r0, #1 pop {r4, r5, r6, r7} bx lr Maybe RV32 should also support LL/SC instructions with two 32-bit registe= rs. Another option would be to split the atomic increment into two parts as=20 suggested by Jakub Jelinek: https://patchwork.ozlabs.org/project/gcc/patch/19c4a81d-6ecd-8c6e-b641-e2= 57c1959baf@suse.cz/#1447334 Another option would be to use library calls if hardware atomics are not=20 available. --=20 embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.huber@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht M=C3=BCnchen Registernummer: HRB 157899 Vertretungsberechtigte Gesch=C3=A4ftsf=C3=BChrer: Peter Rasmussen, Thomas= D=C3=B6rfler Unsere Datenschutzerkl=C3=A4rung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/