From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 72155 invoked by alias); 18 Sep 2019 16:24:50 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 72061 invoked by uid 89); 18 Sep 2019 16:24:37 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-18.4 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3 autolearn=ham version=3.3.1 spammy=HContent-Transfer-Encoding:8bit X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 18 Sep 2019 16:24:36 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 25A61337; Wed, 18 Sep 2019 09:24:27 -0700 (PDT) Received: from [10.2.206.47] (e120808-lin.cambridge.arm.com [10.2.206.47]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8EED53F59C; Wed, 18 Sep 2019 09:24:26 -0700 (PDT) Subject: Re: [PATCH][ARM] Cleanup multiply patterns To: Wilco Dijkstra , GCC Patches , Richard Earnshaw Cc: nd References: From: Kyrill Tkachov Message-ID: Date: Wed, 18 Sep 2019 16:24:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit X-SW-Source: 2019-09/txt/msg01110.txt.bz2 Hi Wilco, On 9/9/19 6:07 PM, Wilco Dijkstra wrote: > ping > > > Cleanup the 32-bit multiply patterns.  Merge the pre-Armv6 with the Armv6 >  patterns, remove useless alternatives and order the accumulator operands >  to prefer MLA Ra, Rb, Rc, Ra whenever feasible. > >  Bootstrap OK on armhf, regress passes. > >  ChangeLog: >  2019-09-03  Wilco Dijkstra  > >          * config/arm/arm.md (arm_mulsi3): Remove pattern. >          (arm_mulsi3_v6): Likewise. >          (mulsi3addsi_v6): Likewise. >          (mulsi3subsi): Likewise. >          (mul): Add new multiply pattern. >          (mla): Likewise. >          (mls): Likewise. > >  -- >  diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md >  index > 66dafdc47b7cfc37c131764e482d47bcaab90538..681358512e88f6823d1b6d59038f387daaec226e > 100644 >  --- a/gcc/config/arm/arm.md >  +++ b/gcc/config/arm/arm.md >  @@ -1594,64 +1594,44 @@ (define_expand "mulsi3" >     "" >   ) > >  -;; Use `&' and then `0' to prevent the operands 0 and 1 being the same >  -(define_insn "*arm_mulsi3" >  -  [(set (match_operand:SI          0 "s_register_operand" "=&r,&r") >  -       (mult:SI (match_operand:SI 2 "s_register_operand" "r,r") >  -                (match_operand:SI 1 "s_register_operand" "%0,r")))] >  -  "TARGET_32BIT && !arm_arch6" >  +;; Use `&' and then `0' to prevent operands 0 and 2 being the same >  +(define_insn "*mul" >  +  [(set (match_operand:SI          0 "s_register_operand" "=l,r,&r,&r") >  +       (mult:SI (match_operand:SI 2 "s_register_operand" "l,r,r,r") >  +                (match_operand:SI 1 "s_register_operand" "%0,r,0,r")))] >  +  "TARGET_32BIT" >     "mul%?\\t%0, %2, %1" >     [(set_attr "type" "mul") >  -   (set_attr "predicable" "yes")] >  -) >  - >  -(define_insn "*arm_mulsi3_v6" >  -  [(set (match_operand:SI          0 "s_register_operand" "=l,l,r") >  -       (mult:SI (match_operand:SI 1 "s_register_operand" "0,l,r") >  -                (match_operand:SI 2 "s_register_operand" "l,0,r")))] >  -  "TARGET_32BIT && arm_arch6" >  -  "mul%?\\t%0, %1, %2" >  -  [(set_attr "type" "mul") >      (set_attr "predicable" "yes") >  -   (set_attr "arch" "t2,t2,*") >  +   (set_attr "arch" "t2,v6,nov6,nov6") >      (set_attr "length" "4") >  -   (set_attr "predicable_short_it" "yes,yes,no")] >  +   (set_attr "predicable_short_it" "yes,no,*,*")] >   ) > >  -;; Unnamed templates to match MLA instruction. >  +;; MLA and MLS instruction. Use operand 1 for the accumulator to prefer >  +;; reusing the same register. > >  -(define_insn "*mulsi3addsi" >  -  [(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r") >  +(define_insn "*mla" >  +  [(set (match_operand:SI 0 "s_register_operand" "=r,&r,&r,&r") >           (plus:SI >  -         (mult:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r") >  -                  (match_operand:SI 1 "s_register_operand" "%0,r,0,r")) >  -         (match_operand:SI 3 "s_register_operand" "r,r,0,0")))] >  -  "TARGET_32BIT && !arm_arch6" >  -  "mla%?\\t%0, %2, %1, %3" >  -  [(set_attr "type" "mla") >  -   (set_attr "predicable" "yes")] >  -) >  - >  -(define_insn "*mulsi3addsi_v6" >  -  [(set (match_operand:SI 0 "s_register_operand" "=r") >  -       (plus:SI >  -         (mult:SI (match_operand:SI 2 "s_register_operand" "r") >  -                  (match_operand:SI 1 "s_register_operand" "r")) >  -         (match_operand:SI 3 "s_register_operand" "r")))] >  -  "TARGET_32BIT && arm_arch6" >  -  "mla%?\\t%0, %2, %1, %3" >  +         (mult:SI (match_operand:SI 3 "s_register_operand" "r,r,r,r") >  +                  (match_operand:SI 2 "s_register_operand" "%r,r,0,r")) >  +         (match_operand:SI 1 "s_register_operand" "r,0,r,r")))] >  +  "TARGET_32BIT" >  +  "mla%?\\t%0, %3, %2, %1" >     [(set_attr "type" "mla") >  -   (set_attr "predicable" "yes")] >  +   (set_attr "predicable" "yes") >  +   (set_attr "arch" "v6,nov6,nov6,nov6")] >   ) > >  -(define_insn "*mulsi3subsi" >  +(define_insn "*mls" >     [(set (match_operand:SI 0 "s_register_operand" "=r") >           (minus:SI >  -         (match_operand:SI 3 "s_register_operand" "r") >  -         (mult:SI (match_operand:SI 2 "s_register_operand" "r") >  -                  (match_operand:SI 1 "s_register_operand" "r"))))] >  +         (match_operand:SI 1 "s_register_operand" "r") >  +         (mult:SI (match_operand:SI 3 "s_register_operand" "r") >  +                  (match_operand:SI 2 "s_register_operand" "r"))))] Looks like we'll want to mark operand 2 here with '%' as well? Looks ok to me otherwise. Thanks, Kyrill >     "TARGET_32BIT && arm_arch_thumb2" >  -  "mls%?\\t%0, %2, %1, %3" >  +  "mls%?\\t%0, %3, %2, %1" >     [(set_attr "type" "mla") >      (set_attr "predicable" "yes")] >   ) >