* [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
@ 2020-08-13 16:12 Carl Love
2020-08-13 18:38 ` Bill Schmidt
2020-08-14 21:33 ` Segher Boessenkool
0 siblings, 2 replies; 20+ messages in thread
From: Carl Love @ 2020-08-13 16:12 UTC (permalink / raw)
To: Segher Boessenkool, dje.gcc, gcc-patches, Will Schmidt
Cc: Bill Schmidt, cel, Peter Bergner
GCC maintainers:
The macro expansion for the bfloat convert intrinsics XVCVBF16SP and
XVCVSPBF16 need to be restricted to P10.
The macro expansions BU_P10V_0, BU_P10V_1, BU_P10V_2, BU_P10V_3 expand
the name field as "__builtin_altivec_". These macro expansions are
being used for both VSX and Altivec instructions. There needs to be
separate expansions for VSX with the name field "__builtin_vsx_" and
for Altivec with the name field "__builtin_altivec_".
The following patch creates new macro expansions BU_P10V_VSX_# and
BU_P10V_AV_# for the VSX and Altivec instructions respectively. The
new names are consistent with the P8 and P9 naming convention for the
VSX and Altivec instructions.
The macro expansion for XVCVBF16SP and XVCVSPBF16 is changed from
BU_VSX_1 to BU_P10V_VSX_1 to restrict it to P10 and beyond. Also MISC
is changed to CONST in the macro expansion call.
The side effect of creating the macro expansions for VSX and Altivec is
it changes all of the expanded names. The patch fixes all the uses of
the expanded names as needed for the new VSX and Altivec macros.
The patch has been run on
powerpc64le-unknown-linux-gnu (Power 8 LE)
powerpc64le-unknown-linux-gnu (Power 9 LE)
with no regressions.
Please let me know if the patch is acceptable for trunk.
Carl Love
-----------------------------------------------------------------
[PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
gcc/ChangeLog
2020-08-12 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000-builtin.def (BU_P10V_0, BU_P10V_1,
BU_P10V_2, BU_P10V_3): Rename BU_P10V_VSX_0, BU_P10V_VSX_1,
BU_P10V_VSX_2, BU_P10V_VSX_3 respectively.
(BU_P10V_4): Remove.
(BU_P10V_AV_0, BU_P10V_AV_1, BU_P10V_AV_2, BU_P10V_AV_3, BU_P10V_AV_4):
New definitions for Power 10 Altivec macros.
(VSTRIBR, VSTRIHR, VSTRIBL, VSTRIHL, VSTRIBR_P, VSTRIHR_P,
VSTRIBL_P, VSTRIHL_P, MTVSRBM, MTVSRHM, MTVSRWM, MTVSRDM, MTVSRQM,
VEXPANDMB, VEXPANDMH, VEXPANDMW, VEXPANDMD, VEXPANDMQ, VEXTRACTMB,
VEXTRACTMH, VEXTRACTMW, VEXTRACTMD, VEXTRACTMQ): Replace macro
expansion BU_P10V_1 with BU_P10V_AV_1.
(VCLRLB, VCLRRB, VCFUGED, VCLZDM, VCTZDM, VPDEPD, VPEXTD, VGNB,
VCNTMBB, VCNTMBH, VCNTMBW, VCNTMBD): Replace macro expansion
BU_P10V_2 with BU_P10V_AV_2.
(VEXTRACTBL, VEXTRACTHL, VEXTRACTWL, VEXTRACTDL, VEXTRACTBR, VEXTRACTHR,
VEXTRACTWR, VEXTRACTDR, VINSERTGPRBL, VINSERTGPRHL, VINSERTGPRWL,
VINSERTGPRDL, VINSERTVPRBL, VINSERTVPRHL, VINSERTVPRWL, VINSERTGPRBR,
VINSERTGPRHR, VINSERTGPRWR, VINSERTGPRDR, VINSERTVPRBR, VINSERTVPRHR,
VINSERTVPRWR, VREPLACE_ELT_V4SI, VREPLACE_ELT_UV4SI, VREPLACE_ELT_V2DF,
VREPLACE_ELT_V4SF, VREPLACE_ELT_V2DI, VREPLACE_ELT_UV2DI, VREPLACE_UN_V4SI,
VREPLACE_UN_UV4SI, VREPLACE_UN_V4SF, VREPLACE_UN_V2DI, VREPLACE_UN_UV2DI,
VREPLACE_UN_V2DF, VSLDB_V16QI, VSLDB_V8HI, VSLDB_V4SI, VSLDB_V2DI,
VSRDB_V16QI, VSRDB_V8HI, VSRDB_V4SI, VSRDB_V2DI): Replace macro expansion
BU_P10V_3 with BU_P10V_AV_3.
(VXXSPLTIW_V4SI, VXXSPLTIW_V4SF, VXXSPLTID): Replace macro expansion
BU_P10V_1 with BU_P10V_AV_1.
(XXGENPCVM_V16QI, XXGENPCVM_V8HI, XXGENPCVM_V4SI, XXGENPCVM_V2DI):
Replace macro expansion BU_P10V_2 with BU_P10V_VSX_2.
(VXXSPLTI32DX_V4SI, VXXSPLTI32DX_V4SF, VXXBLEND_V16QI, VXXBLEND_V8HI,
VXXBLEND_V4SI, VXXBLEND_V2DI, VXXBLEND_V4SF, VXXBLEND_V2DF): Replace macor
expansion BU_P10V_3 with BU_P10V_VSX_3.
(XXEVAL, VXXPERMX): Replace macro expansion BU_P10V_4 with BU_P10V_VSX_4.
(XVCVBF16SP, XVCVSPBF16): Replace macro expansion BU_VSX_1 with
BU_P10V_VSX_1. Also change MISC to CONST.
* config/rs6000/rs6000-c.c: (P10_BUILTIN_VXXPERMX): Replace with
P10V_BUILTIN_VXXPERMX.
(P10_BUILTIN_VCLRLB, P10_BUILTIN_VCLRLB, P10_BUILTIN_VCLRRB,
P10_BUILTIN_VGNB, P10_BUILTIN_XXEVAL, P10_BUILTIN_VXXPERMX,
P10_BUILTIN_VEXTRACTBL, P10_BUILTIN_VEXTRACTHL, P10_BUILTIN_VEXTRACTWL,
P10_BUILTIN_VEXTRACTDL, P10_BUILTIN_VINSERTGPRHL,
P10_BUILTIN_VINSERTGPRWL, P10_BUILTIN_VINSERTGPRDL,
P10_BUILTIN_VINSERTVPRBL, P10_BUILTIN_VINSERTVPRHL,
P10_BUILTIN_VEXTRACTBR, P10_BUILTIN_VEXTRACTHR,
P10_BUILTIN_VEXTRACTWR, P10_BUILTIN_VEXTRACTDR,
P10_BUILTIN_VINSERTGPRBR, P10_BUILTIN_VINSERTGPRHR,
P10_BUILTIN_VINSERTGPRWR, P10_BUILTIN_VINSERTGPRDR,
P10_BUILTIN_VINSERTVPRBR, P10_BUILTIN_VINSERTVPRHR,
P10_BUILTIN_VINSERTVPRWR, P10_BUILTIN_VREPLACE_ELT_UV4SI,
P10_BUILTIN_VREPLACE_ELT_V4SI, P10_BUILTIN_VREPLACE_ELT_UV2DI,
P10_BUILTIN_VREPLACE_ELT_V2DI, P10_BUILTIN_VREPLACE_ELT_V2DF,
P10_BUILTIN_VREPLACE_UN_UV4SI, P10_BUILTIN_VREPLACE_UN_V4SI,
P10_BUILTIN_VREPLACE_UN_V4SF, P10_BUILTIN_VREPLACE_UN_UV2DI,
P10_BUILTIN_VREPLACE_UN_V2DI, P10_BUILTIN_VREPLACE_UN_V2DF,
P10_BUILTIN_VSLDB_V16QI, P10_BUILTIN_VSLDB_V16QI,
P10_BUILTIN_VSLDB_V8HI, P10_BUILTIN_VSLDB_V4SI,
P10_BUILTIN_VSLDB_V2DI, P10_BUILTIN_VXXSPLTIW_V4SI,
P10_BUILTIN_VXXSPLTIW_V4SF, P10_BUILTIN_VXXSPLTID,
P10_BUILTIN_VXXSPLTI32DX_V4SI, P10_BUILTIN_VXXSPLTI32DX_V4SF,
P10_BUILTIN_VXXBLEND_V16QI, P10_BUILTIN_VXXBLEND_V8HI,
P10_BUILTIN_VXXBLEND_V4SI, P10_BUILTIN_VXXBLEND_V2DI,
P10_BUILTIN_VXXBLEND_V4SF, P10_BUILTIN_VXXBLEND_V2DF,
P10_BUILTIN_VSRDB_V16QI, P10_BUILTIN_VSRDB_V8HI,
P10_BUILTIN_VSRDB_V4SI, P10_BUILTIN_VSRDB_V2DI,
P10_BUILTIN_VSTRIBL, P10_BUILTIN_VSTRIHL,
P10_BUILTIN_VSTRIBL_P, P10_BUILTIN_VSTRIHL_P,
P10_BUILTIN_VSTRIBR, P10_BUILTIN_VSTRIHR,
P10_BUILTIN_VSTRIBR_P, P10_BUILTIN_VSTRIHR_P,
P10_BUILTIN_MTVSRBM, P10_BUILTIN_MTVSRHM,
P10_BUILTIN_MTVSRWM, P10_BUILTIN_MTVSRDM,
P10_BUILTIN_MTVSRQM, P10_BUILTIN_VCNTMBB,
P10_BUILTIN_VCNTMBH, P10_BUILTIN_VCNTMBW,
P10_BUILTIN_VCNTMBD, P10_BUILTIN_VEXPANDMB,
P10_BUILTIN_VEXPANDMH, P10_BUILTIN_VEXPANDMW,
P10_BUILTIN_VEXPANDMD, P10_BUILTIN_VEXPANDMQ,
P10_BUILTIN_VEXTRACTMB, P10_BUILTIN_VEXTRACTMH,
P10_BUILTIN_VEXTRACTMW, P10_BUILTIN_VEXTRACTMD,
P10_BUILTIN_VEXTRACTMQ, P10_BUILTIN_XVTLSBB_ZEROS,
P10_BUILTIN_XVTLSBB_ONES): Replace with
P10V_BUILTIN_VCLRLB, P10V_BUILTIN_VCLRLB, P10V_BUILTIN_VCLRRB,
P10V_BUILTIN_VGNB, P10V_BUILTIN_XXEVAL, P10V_BUILTIN_VXXPERMX,
P10V_BUILTIN_VEXTRACTBL, P10V_BUILTIN_VEXTRACTHL, P10V_BUILTIN_VEXTRACTWL,
P10V_BUILTIN_VEXTRACTDL, P10V_BUILTIN_VINSERTGPRHL,
P10V_BUILTIN_VINSERTGPRWL, P10V_BUILTIN_VINSERTGPRDL,
P10V_BUILTIN_VINSERTVPRBL,P10V_BUILTIN_VINSERTVPRHL,
P10V_BUILTIN_VEXTRACTBR, P10V_BUILTIN_VEXTRACTHR
P10V_BUILTIN_VEXTRACTWR, P10V_BUILTIN_VEXTRACTDR,
P10V_BUILTIN_VINSERTGPRBR, P10V_BUILTIN_VINSERTGPRHR,
P10V_BUILTIN_VINSERTGPRWR, P10V_BUILTIN_VINSERTGPRDR,
P10V_BUILTIN_VINSERTVPRBR, P10V_BUILTIN_VINSERTVPRHR,
P10V_BUILTIN_VINSERTVPRWR, P10V_BUILTIN_VREPLACE_ELT_UV4SI,
P10V_BUILTIN_VREPLACE_ELT_V4SI, P10V_BUILTIN_VREPLACE_ELT_UV2DI,
P10V_BUILTIN_VREPLACE_ELT_V2DI, P10V_BUILTIN_VREPLACE_ELT_V2DF,
P10V_BUILTIN_VREPLACE_UN_UV4SI, P10V_BUILTIN_VREPLACE_UN_V4SI,
P10V_BUILTIN_VREPLACE_UN_V4SF, P10V_BUILTIN_VREPLACE_UN_UV2DI,
P10V_BUILTIN_VREPLACE_UN_V2DI, P10V_BUILTIN_VREPLACE_UN_V2DF,
P10V_BUILTIN_VSLDB_V16QI, P10V_BUILTIN_VSLDB_V16QI,
P10V_BUILTIN_VSLDB_V8HI, P10V_BUILTIN_VSLDB_V4SI,
P10V_BUILTIN_VSLDB_V2DI, P10V_BUILTIN_VXXSPLTIW_V4SI,
P10V_BUILTIN_VXXSPLTIW_V4SF, P10V_BUILTIN_VXXSPLTID,
P10V_BUILTIN_VXXSPLTI32DX_V4SI, P10V_BUILTIN_VXXSPLTI32DX_V4SF,
P10V_BUILTIN_VXXBLEND_V16QI, P10V_BUILTIN_VXXBLEND_V8HI,
P10V_BUILTIN_VXXBLEND_V4SI, P10V_BUILTIN_VXXBLEND_V2DI,
P10V_BUILTIN_VXXBLEND_V4SF, P10V_BUILTIN_VXXBLEND_V2DF,
P10V_BUILTIN_VSRDB_V16QI, P10V_BUILTIN_VSRDB_V8HI,
P10V_BUILTIN_VSRDB_V4SI, P10V_BUILTIN_VSRDB_V2DI,
P10V_BUILTIN_VSTRIBL, P10V_BUILTIN_VSTRIHL,
P10V_BUILTIN_VSTRIBL_P, P10V_BUILTIN_VSTRIHL_P,
P10V_BUILTIN_VSTRIBR, P10V_BUILTIN_VSTRIHR,
P10V_BUILTIN_VSTRIBR_P, P10V_BUILTIN_VSTRIHR_P,
P10V_BUILTIN_MTVSRBM, P10V_BUILTIN_MTVSRHM,
P10V_BUILTIN_MTVSRWM, P10V_BUILTIN_MTVSRDM,
P10V_BUILTIN_MTVSRQM, P10V_BUILTIN_VCNTMBB,
P10V_BUILTIN_VCNTMBH, P10V_BUILTIN_VCNTMBW,
P10V_BUILTIN_VCNTMBD, P10V_BUILTIN_VEXPANDMB,
P10V_BUILTIN_VEXPANDMH, P10V_BUILTIN_VEXPANDMW,
P10V_BUILTIN_VEXPANDMD, P10V_BUILTIN_VEXPANDMQ,
P10V_BUILTIN_VEXTRACTMB, P10V_BUILTIN_VEXTRACTMH,
P10V_BUILTIN_VEXTRACTMW, P10V_BUILTIN_VEXTRACTMD,
P10V_BUILTIN_VEXTRACTMQ, P10V_BUILTIN_XVTLSBB_ZEROS,
P10V_BUILTIN_XVTLSBB_ONES respectively.
* config/rs6000/rs6000-call.c: Ditto above, change P10_BUILTIN_name to
P10V_BUILTIN_name.
(P10_BUILTIN_XVCVSPBF16, P10_BUILTIN_XVCVBF16SP): Change to
P10V_BUILTIN_XVCVSPBF16, P10V_BUILTIN_XVCVBF16SP respectively.
---
gcc/config/rs6000/rs6000-builtin.def | 303 +++++++++++-----------
gcc/config/rs6000/rs6000-c.c | 6 +-
gcc/config/rs6000/rs6000-call.c | 360 +++++++++++++--------------
3 files changed, 347 insertions(+), 322 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index f9f0fece549..97b16dc1079 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1019,55 +1019,46 @@
| RS6000_BTC_BINARY), \
CODE_FOR_ ## ICODE) /* ICODE */
-/* For builtins for power10 vector instructions that are encoded as altivec
- instructions, use __builtin_altivec_ as the builtin name. */
+/* Power 10 VSX builtins */
-#define BU_P10V_0(ENUM, NAME, ATTR, ICODE) \
+#define BU_P10V_VSX_0(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_0 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
- "__builtin_altivec_" NAME, /* NAME */ \
+ "__builtin_vsx_" NAME, /* NAME */ \
RS6000_BTM_P10, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_SPECIAL), \
CODE_FOR_ ## ICODE) /* ICODE */
-#define BU_P10V_1(ENUM, NAME, ATTR, ICODE) \
- RS6000_BUILTIN_1 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
- "__builtin_altivec_" NAME, /* NAME */ \
+#define BU_P10V_VSX_1(ENUM, NAME, ATTR, ICODE) \
+ RS6000_BUILTIN_1 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
+ "__builtin_vsx_" NAME, /* NAME */ \
RS6000_BTM_P10, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_UNARY), \
CODE_FOR_ ## ICODE) /* ICODE */
-#define BU_P10V_2(ENUM, NAME, ATTR, ICODE) \
- RS6000_BUILTIN_2 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
- "__builtin_altivec_" NAME, /* NAME */ \
+#define BU_P10V_VSX_2(ENUM, NAME, ATTR, ICODE) \
+ RS6000_BUILTIN_2 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
+ "__builtin_vsx_" NAME, /* NAME */ \
RS6000_BTM_P10, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_BINARY), \
CODE_FOR_ ## ICODE) /* ICODE */
-#define BU_P10V_3(ENUM, NAME, ATTR, ICODE) \
- RS6000_BUILTIN_3 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
- "__builtin_altivec_" NAME, /* NAME */ \
+#define BU_P10V_VSX_3(ENUM, NAME, ATTR, ICODE) \
+ RS6000_BUILTIN_3 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
+ "__builtin_vsx_" NAME, /* NAME */ \
RS6000_BTM_P10, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
| RS6000_BTC_TERNARY), \
CODE_FOR_ ## ICODE) /* ICODE */
-#define BU_P10V_4(ENUM, NAME, ATTR, ICODE) \
- RS6000_BUILTIN_4 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
- "__builtin_altivec_" NAME, /* NAME */ \
- RS6000_BTM_P10, /* MASK */ \
- (RS6000_BTC_ ## ATTR /* ATTR */ \
- | RS6000_BTC_QUATERNARY), \
- CODE_FOR_ ## ICODE) /* ICODE */
-
-#define BU_P10_VSX_1(ENUM, NAME, ATTR, ICODE) \
- RS6000_BUILTIN_1 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
+#define BU_P10V_VSX_4(ENUM, NAME, ATTR, ICODE) \
+ RS6000_BUILTIN_4 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
"__builtin_vsx_" NAME, /* NAME */ \
RS6000_BTM_P10, /* MASK */ \
(RS6000_BTC_ ## ATTR /* ATTR */ \
- | RS6000_BTC_UNARY), \
+ | RS6000_BTC_QUATERNARY), \
CODE_FOR_ ## ICODE) /* ICODE */
#define BU_P10_OVERLOAD_1(ENUM, NAME) \
@@ -1154,6 +1145,40 @@
CODE_FOR_ ## ICODE) /* ICODE */
#endif
+/* Power 10 Altivec builtins */
+
+#define BU_P10V_AV_0(ENUM, NAME, ATTR, ICODE) \
+ RS6000_BUILTIN_0 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
+ "__builtin_altivec_" NAME, /* NAME */ \
+ RS6000_BTM_P10, /* MASK */ \
+ (RS6000_BTC_ ## ATTR /* ATTR */ \
+ | RS6000_BTC_SPECIAL), \
+ CODE_FOR_ ## ICODE) /* ICODE */
+
+#define BU_P10V_AV_1(ENUM, NAME, ATTR, ICODE) \
+ RS6000_BUILTIN_1 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
+ "__builtin_altivec_" NAME, /* NAME */ \
+ RS6000_BTM_P10, /* MASK */ \
+ (RS6000_BTC_ ## ATTR /* ATTR */ \
+ | RS6000_BTC_UNARY), \
+ CODE_FOR_ ## ICODE) /* ICODE */
+
+#define BU_P10V_AV_2(ENUM, NAME, ATTR, ICODE) \
+ RS6000_BUILTIN_2 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
+ "__builtin_altivec_" NAME, /* NAME */ \
+ RS6000_BTM_P10, /* MASK */ \
+ (RS6000_BTC_ ## ATTR /* ATTR */ \
+ | RS6000_BTC_BINARY), \
+ CODE_FOR_ ## ICODE) /* ICODE */
+
+#define BU_P10V_AV_3(ENUM, NAME, ATTR, ICODE) \
+ RS6000_BUILTIN_3 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
+ "__builtin_altivec_" NAME, /* NAME */ \
+ RS6000_BTM_P10, /* MASK */ \
+ (RS6000_BTC_ ## ATTR /* ATTR */ \
+ | RS6000_BTC_TERNARY), \
+ CODE_FOR_ ## ICODE) /* ICODE */
+
\f
/* Insure 0 is not a legitimate index. */
BU_SPECIAL_X (RS6000_BUILTIN_NONE, NULL, 0, RS6000_BTC_MISC)
@@ -2710,119 +2735,119 @@ BU_P10_MISC_2 (PDEPD, "pdepd", CONST, pdepd)
BU_P10_MISC_2 (PEXTD, "pextd", CONST, pextd)
/* Builtins for vector instructions added in ISA 3.1 (power10). */
-BU_P10V_2 (VCLRLB, "vclrlb", CONST, vclrlb)
-BU_P10V_2 (VCLRRB, "vclrrb", CONST, vclrrb)
-BU_P10V_2 (VCFUGED, "vcfuged", CONST, vcfuged)
-BU_P10V_2 (VCLZDM, "vclzdm", CONST, vclzdm)
-BU_P10V_2 (VCTZDM, "vctzdm", CONST, vctzdm)
-BU_P10V_2 (VPDEPD, "vpdepd", CONST, vpdepd)
-BU_P10V_2 (VPEXTD, "vpextd", CONST, vpextd)
-BU_P10V_2 (VGNB, "vgnb", CONST, vgnb)
-BU_P10V_4 (XXEVAL, "xxeval", CONST, xxeval)
-BU_P10V_2 (XXGENPCVM_V16QI, "xxgenpcvm_v16qi", CONST, xxgenpcvm_v16qi)
-BU_P10V_2 (XXGENPCVM_V8HI, "xxgenpcvm_v8hi", CONST, xxgenpcvm_v8hi)
-BU_P10V_2 (XXGENPCVM_V4SI, "xxgenpcvm_v4si", CONST, xxgenpcvm_v4si)
-BU_P10V_2 (XXGENPCVM_V2DI, "xxgenpcvm_v2di", CONST, xxgenpcvm_v2di)
-
-BU_P10V_3 (VEXTRACTBL, "vextdubvlx", CONST, vextractlv16qi)
-BU_P10V_3 (VEXTRACTHL, "vextduhvlx", CONST, vextractlv8hi)
-BU_P10V_3 (VEXTRACTWL, "vextduwvlx", CONST, vextractlv4si)
-BU_P10V_3 (VEXTRACTDL, "vextddvlx", CONST, vextractlv2di)
-
-BU_P10V_3 (VEXTRACTBR, "vextdubvhx", CONST, vextractrv16qi)
-BU_P10V_3 (VEXTRACTHR, "vextduhvhx", CONST, vextractrv8hi)
-BU_P10V_3 (VEXTRACTWR, "vextduwvhx", CONST, vextractrv4si)
-BU_P10V_3 (VEXTRACTDR, "vextddvhx", CONST, vextractrv2di)
-
-BU_P10V_3 (VINSERTGPRBL, "vinsgubvlx", CONST, vinsertgl_v16qi)
-BU_P10V_3 (VINSERTGPRHL, "vinsguhvlx", CONST, vinsertgl_v8hi)
-BU_P10V_3 (VINSERTGPRWL, "vinsguwvlx", CONST, vinsertgl_v4si)
-BU_P10V_3 (VINSERTGPRDL, "vinsgudvlx", CONST, vinsertgl_v2di)
-BU_P10V_3 (VINSERTVPRBL, "vinsvubvlx", CONST, vinsertvl_v16qi)
-BU_P10V_3 (VINSERTVPRHL, "vinsvuhvlx", CONST, vinsertvl_v8hi)
-BU_P10V_3 (VINSERTVPRWL, "vinsvuwvlx", CONST, vinsertvl_v4si)
-
-BU_P10V_3 (VINSERTGPRBR, "vinsgubvrx", CONST, vinsertgr_v16qi)
-BU_P10V_3 (VINSERTGPRHR, "vinsguhvrx", CONST, vinsertgr_v8hi)
-BU_P10V_3 (VINSERTGPRWR, "vinsguwvrx", CONST, vinsertgr_v4si)
-BU_P10V_3 (VINSERTGPRDR, "vinsgudvrx", CONST, vinsertgr_v2di)
-BU_P10V_3 (VINSERTVPRBR, "vinsvubvrx", CONST, vinsertvr_v16qi)
-BU_P10V_3 (VINSERTVPRHR, "vinsvuhvrx", CONST, vinsertvr_v8hi)
-BU_P10V_3 (VINSERTVPRWR, "vinsvuwvrx", CONST, vinsertvr_v4si)
-
-BU_P10V_3 (VREPLACE_ELT_V4SI, "vreplace_v4si", CONST, vreplace_elt_v4si)
-BU_P10V_3 (VREPLACE_ELT_UV4SI, "vreplace_uv4si", CONST, vreplace_elt_v4si)
-BU_P10V_3 (VREPLACE_ELT_V4SF, "vreplace_v4sf", CONST, vreplace_elt_v4sf)
-BU_P10V_3 (VREPLACE_ELT_V2DI, "vreplace_v2di", CONST, vreplace_elt_v2di)
-BU_P10V_3 (VREPLACE_ELT_UV2DI, "vreplace_uv2di", CONST, vreplace_elt_v2di)
-BU_P10V_3 (VREPLACE_ELT_V2DF, "vreplace_v2df", CONST, vreplace_elt_v2df)
-
-BU_P10V_3 (VREPLACE_UN_V4SI, "vreplace_un_v4si", CONST, vreplace_un_v4si)
-BU_P10V_3 (VREPLACE_UN_UV4SI, "vreplace_un_uv4si", CONST, vreplace_un_v4si)
-BU_P10V_3 (VREPLACE_UN_V4SF, "vreplace_un_v4sf", CONST, vreplace_un_v4sf)
-BU_P10V_3 (VREPLACE_UN_V2DI, "vreplace_un_v2di", CONST, vreplace_un_v2di)
-BU_P10V_3 (VREPLACE_UN_UV2DI, "vreplace_un_uv2di", CONST, vreplace_un_v2di)
-BU_P10V_3 (VREPLACE_UN_V2DF, "vreplace_un_v2df", CONST, vreplace_un_v2df)
-
-BU_P10V_3 (VSLDB_V16QI, "vsldb_v16qi", CONST, vsldb_v16qi)
-BU_P10V_3 (VSLDB_V8HI, "vsldb_v8hi", CONST, vsldb_v8hi)
-BU_P10V_3 (VSLDB_V4SI, "vsldb_v4si", CONST, vsldb_v4si)
-BU_P10V_3 (VSLDB_V2DI, "vsldb_v2di", CONST, vsldb_v2di)
-
-BU_P10V_3 (VSRDB_V16QI, "vsrdb_v16qi", CONST, vsrdb_v16qi)
-BU_P10V_3 (VSRDB_V8HI, "vsrdb_v8hi", CONST, vsrdb_v8hi)
-BU_P10V_3 (VSRDB_V4SI, "vsrdb_v4si", CONST, vsrdb_v4si)
-BU_P10V_3 (VSRDB_V2DI, "vsrdb_v2di", CONST, vsrdb_v2di)
-
-BU_P10V_1 (VXXSPLTIW_V4SI, "vxxspltiw_v4si", CONST, xxspltiw_v4si)
-BU_P10V_1 (VXXSPLTIW_V4SF, "vxxspltiw_v4sf", CONST, xxspltiw_v4sf)
-
-BU_P10V_1 (VXXSPLTID, "vxxspltidp", CONST, xxspltidp_v2df)
-
-BU_P10V_3 (VXXSPLTI32DX_V4SI, "vxxsplti32dx_v4si", CONST, xxsplti32dx_v4si)
-BU_P10V_3 (VXXSPLTI32DX_V4SF, "vxxsplti32dx_v4sf", CONST, xxsplti32dx_v4sf)
-
-BU_P10V_3 (VXXBLEND_V16QI, "xxblend_v16qi", CONST, xxblend_v16qi)
-BU_P10V_3 (VXXBLEND_V8HI, "xxblend_v8hi", CONST, xxblend_v8hi)
-BU_P10V_3 (VXXBLEND_V4SI, "xxblend_v4si", CONST, xxblend_v4si)
-BU_P10V_3 (VXXBLEND_V2DI, "xxblend_v2di", CONST, xxblend_v2di)
-BU_P10V_3 (VXXBLEND_V4SF, "xxblend_v4sf", CONST, xxblend_v4sf)
-BU_P10V_3 (VXXBLEND_V2DF, "xxblend_v2df", CONST, xxblend_v2df)
-
-BU_P10V_4 (VXXPERMX, "xxpermx", CONST, xxpermx)
-
-BU_P10V_1 (VSTRIBR, "vstribr", CONST, vstrir_v16qi)
-BU_P10V_1 (VSTRIHR, "vstrihr", CONST, vstrir_v8hi)
-BU_P10V_1 (VSTRIBL, "vstribl", CONST, vstril_v16qi)
-BU_P10V_1 (VSTRIHL, "vstrihl", CONST, vstril_v8hi)
-
-BU_P10V_1 (VSTRIBR_P, "vstribr_p", CONST, vstrir_p_v16qi)
-BU_P10V_1 (VSTRIHR_P, "vstrihr_p", CONST, vstrir_p_v8hi)
-BU_P10V_1 (VSTRIBL_P, "vstribl_p", CONST, vstril_p_v16qi)
-BU_P10V_1 (VSTRIHL_P, "vstrihl_p", CONST, vstril_p_v8hi)
-
-BU_P10_VSX_1 (XVTLSBB_ZEROS, "xvtlsbb_all_zeros", CONST, xvtlsbbz)
-BU_P10_VSX_1 (XVTLSBB_ONES, "xvtlsbb_all_ones", CONST, xvtlsbbo)
-
-BU_P10V_1 (MTVSRBM, "mtvsrbm", CONST, vec_mtvsr_v16qi)
-BU_P10V_1 (MTVSRHM, "mtvsrhm", CONST, vec_mtvsr_v8hi)
-BU_P10V_1 (MTVSRWM, "mtvsrwm", CONST, vec_mtvsr_v4si)
-BU_P10V_1 (MTVSRDM, "mtvsrdm", CONST, vec_mtvsr_v2di)
-BU_P10V_1 (MTVSRQM, "mtvsrqm", CONST, vec_mtvsr_v1ti)
-BU_P10V_2 (VCNTMBB, "cntmbb", CONST, vec_cntmb_v16qi)
-BU_P10V_2 (VCNTMBH, "cntmbh", CONST, vec_cntmb_v8hi)
-BU_P10V_2 (VCNTMBW, "cntmbw", CONST, vec_cntmb_v4si)
-BU_P10V_2 (VCNTMBD, "cntmbd", CONST, vec_cntmb_v2di)
-BU_P10V_1 (VEXPANDMB, "vexpandmb", CONST, vec_expand_v16qi)
-BU_P10V_1 (VEXPANDMH, "vexpandmh", CONST, vec_expand_v8hi)
-BU_P10V_1 (VEXPANDMW, "vexpandmw", CONST, vec_expand_v4si)
-BU_P10V_1 (VEXPANDMD, "vexpandmd", CONST, vec_expand_v2di)
-BU_P10V_1 (VEXPANDMQ, "vexpandmq", CONST, vec_expand_v1ti)
-BU_P10V_1 (VEXTRACTMB, "vextractmb", CONST, vec_extract_v16qi)
-BU_P10V_1 (VEXTRACTMH, "vextractmh", CONST, vec_extract_v8hi)
-BU_P10V_1 (VEXTRACTMW, "vextractmw", CONST, vec_extract_v4si)
-BU_P10V_1 (VEXTRACTMD, "vextractmd", CONST, vec_extract_v2di)
-BU_P10V_1 (VEXTRACTMQ, "vextractmq", CONST, vec_extract_v1ti)
+BU_P10V_AV_2 (VCLRLB, "vclrlb", CONST, vclrlb)
+BU_P10V_AV_2 (VCLRRB, "vclrrb", CONST, vclrrb)
+BU_P10V_AV_2 (VCFUGED, "vcfuged", CONST, vcfuged)
+BU_P10V_AV_2 (VCLZDM, "vclzdm", CONST, vclzdm)
+BU_P10V_AV_2 (VCTZDM, "vctzdm", CONST, vctzdm)
+BU_P10V_AV_2 (VPDEPD, "vpdepd", CONST, vpdepd)
+BU_P10V_AV_2 (VPEXTD, "vpextd", CONST, vpextd)
+BU_P10V_AV_2 (VGNB, "vgnb", CONST, vgnb)
+BU_P10V_VSX_4 (XXEVAL, "xxeval", CONST, xxeval)
+BU_P10V_VSX_2 (XXGENPCVM_V16QI, "xxgenpcvm_v16qi", CONST, xxgenpcvm_v16qi)
+BU_P10V_VSX_2 (XXGENPCVM_V8HI, "xxgenpcvm_v8hi", CONST, xxgenpcvm_v8hi)
+BU_P10V_VSX_2 (XXGENPCVM_V4SI, "xxgenpcvm_v4si", CONST, xxgenpcvm_v4si)
+BU_P10V_VSX_2 (XXGENPCVM_V2DI, "xxgenpcvm_v2di", CONST, xxgenpcvm_v2di)
+
+BU_P10V_AV_3 (VEXTRACTBL, "vextdubvlx", CONST, vextractlv16qi)
+BU_P10V_AV_3 (VEXTRACTHL, "vextduhvlx", CONST, vextractlv8hi)
+BU_P10V_AV_3 (VEXTRACTWL, "vextduwvlx", CONST, vextractlv4si)
+BU_P10V_AV_3 (VEXTRACTDL, "vextddvlx", CONST, vextractlv2di)
+
+BU_P10V_AV_3 (VEXTRACTBR, "vextdubvhx", CONST, vextractrv16qi)
+BU_P10V_AV_3 (VEXTRACTHR, "vextduhvhx", CONST, vextractrv8hi)
+BU_P10V_AV_3 (VEXTRACTWR, "vextduwvhx", CONST, vextractrv4si)
+BU_P10V_AV_3 (VEXTRACTDR, "vextddvhx", CONST, vextractrv2di)
+
+BU_P10V_AV_3 (VINSERTGPRBL, "vinsgubvlx", CONST, vinsertgl_v16qi)
+BU_P10V_AV_3 (VINSERTGPRHL, "vinsguhvlx", CONST, vinsertgl_v8hi)
+BU_P10V_AV_3 (VINSERTGPRWL, "vinsguwvlx", CONST, vinsertgl_v4si)
+BU_P10V_AV_3 (VINSERTGPRDL, "vinsgudvlx", CONST, vinsertgl_v2di)
+BU_P10V_AV_3 (VINSERTVPRBL, "vinsvubvlx", CONST, vinsertvl_v16qi)
+BU_P10V_AV_3 (VINSERTVPRHL, "vinsvuhvlx", CONST, vinsertvl_v8hi)
+BU_P10V_AV_3 (VINSERTVPRWL, "vinsvuwvlx", CONST, vinsertvl_v4si)
+
+BU_P10V_AV_3 (VINSERTGPRBR, "vinsgubvrx", CONST, vinsertgr_v16qi)
+BU_P10V_AV_3 (VINSERTGPRHR, "vinsguhvrx", CONST, vinsertgr_v8hi)
+BU_P10V_AV_3 (VINSERTGPRWR, "vinsguwvrx", CONST, vinsertgr_v4si)
+BU_P10V_AV_3 (VINSERTGPRDR, "vinsgudvrx", CONST, vinsertgr_v2di)
+BU_P10V_AV_3 (VINSERTVPRBR, "vinsvubvrx", CONST, vinsertvr_v16qi)
+BU_P10V_AV_3 (VINSERTVPRHR, "vinsvuhvrx", CONST, vinsertvr_v8hi)
+BU_P10V_AV_3 (VINSERTVPRWR, "vinsvuwvrx", CONST, vinsertvr_v4si)
+
+BU_P10V_AV_3 (VREPLACE_ELT_V4SI, "vreplace_v4si", CONST, vreplace_elt_v4si)
+BU_P10V_AV_3 (VREPLACE_ELT_UV4SI, "vreplace_uv4si", CONST, vreplace_elt_v4si)
+BU_P10V_AV_3 (VREPLACE_ELT_V4SF, "vreplace_v4sf", CONST, vreplace_elt_v4sf)
+BU_P10V_AV_3 (VREPLACE_ELT_V2DI, "vreplace_v2di", CONST, vreplace_elt_v2di)
+BU_P10V_AV_3 (VREPLACE_ELT_UV2DI, "vreplace_uv2di", CONST, vreplace_elt_v2di)
+BU_P10V_AV_3 (VREPLACE_ELT_V2DF, "vreplace_v2df", CONST, vreplace_elt_v2df)
+
+BU_P10V_AV_3 (VREPLACE_UN_V4SI, "vreplace_un_v4si", CONST, vreplace_un_v4si)
+BU_P10V_AV_3 (VREPLACE_UN_UV4SI, "vreplace_un_uv4si", CONST, vreplace_un_v4si)
+BU_P10V_AV_3 (VREPLACE_UN_V4SF, "vreplace_un_v4sf", CONST, vreplace_un_v4sf)
+BU_P10V_AV_3 (VREPLACE_UN_V2DI, "vreplace_un_v2di", CONST, vreplace_un_v2di)
+BU_P10V_AV_3 (VREPLACE_UN_UV2DI, "vreplace_un_uv2di", CONST, vreplace_un_v2di)
+BU_P10V_AV_3 (VREPLACE_UN_V2DF, "vreplace_un_v2df", CONST, vreplace_un_v2df)
+
+BU_P10V_AV_3 (VSLDB_V16QI, "vsldb_v16qi", CONST, vsldb_v16qi)
+BU_P10V_AV_3 (VSLDB_V8HI, "vsldb_v8hi", CONST, vsldb_v8hi)
+BU_P10V_AV_3 (VSLDB_V4SI, "vsldb_v4si", CONST, vsldb_v4si)
+BU_P10V_AV_3 (VSLDB_V2DI, "vsldb_v2di", CONST, vsldb_v2di)
+
+BU_P10V_AV_3 (VSRDB_V16QI, "vsrdb_v16qi", CONST, vsrdb_v16qi)
+BU_P10V_AV_3 (VSRDB_V8HI, "vsrdb_v8hi", CONST, vsrdb_v8hi)
+BU_P10V_AV_3 (VSRDB_V4SI, "vsrdb_v4si", CONST, vsrdb_v4si)
+BU_P10V_AV_3 (VSRDB_V2DI, "vsrdb_v2di", CONST, vsrdb_v2di)
+
+BU_P10V_VSX_1 (VXXSPLTIW_V4SI, "vxxspltiw_v4si", CONST, xxspltiw_v4si)
+BU_P10V_VSX_1 (VXXSPLTIW_V4SF, "vxxspltiw_v4sf", CONST, xxspltiw_v4sf)
+
+BU_P10V_VSX_1 (VXXSPLTID, "vxxspltidp", CONST, xxspltidp_v2df)
+
+BU_P10V_VSX_3 (VXXSPLTI32DX_V4SI, "vxxsplti32dx_v4si", CONST, xxsplti32dx_v4si)
+BU_P10V_VSX_3 (VXXSPLTI32DX_V4SF, "vxxsplti32dx_v4sf", CONST, xxsplti32dx_v4sf)
+
+BU_P10V_VSX_3 (VXXBLEND_V16QI, "xxblend_v16qi", CONST, xxblend_v16qi)
+BU_P10V_VSX_3 (VXXBLEND_V8HI, "xxblend_v8hi", CONST, xxblend_v8hi)
+BU_P10V_VSX_3 (VXXBLEND_V4SI, "xxblend_v4si", CONST, xxblend_v4si)
+BU_P10V_VSX_3 (VXXBLEND_V2DI, "xxblend_v2di", CONST, xxblend_v2di)
+BU_P10V_VSX_3 (VXXBLEND_V4SF, "xxblend_v4sf", CONST, xxblend_v4sf)
+BU_P10V_VSX_3 (VXXBLEND_V2DF, "xxblend_v2df", CONST, xxblend_v2df)
+
+BU_P10V_VSX_4 (VXXPERMX, "xxpermx", CONST, xxpermx)
+
+BU_P10V_AV_1 (VSTRIBR, "vstribr", CONST, vstrir_v16qi)
+BU_P10V_AV_1 (VSTRIHR, "vstrihr", CONST, vstrir_v8hi)
+BU_P10V_AV_1 (VSTRIBL, "vstribl", CONST, vstril_v16qi)
+BU_P10V_AV_1 (VSTRIHL, "vstrihl", CONST, vstril_v8hi)
+
+BU_P10V_AV_1 (VSTRIBR_P, "vstribr_p", CONST, vstrir_p_v16qi)
+BU_P10V_AV_1 (VSTRIHR_P, "vstrihr_p", CONST, vstrir_p_v8hi)
+BU_P10V_AV_1 (VSTRIBL_P, "vstribl_p", CONST, vstril_p_v16qi)
+BU_P10V_AV_1 (VSTRIHL_P, "vstrihl_p", CONST, vstril_p_v8hi)
+
+BU_P10V_VSX_1 (XVTLSBB_ZEROS, "xvtlsbb_all_zeros", CONST, xvtlsbbz)
+BU_P10V_VSX_1 (XVTLSBB_ONES, "xvtlsbb_all_ones", CONST, xvtlsbbo)
+
+BU_P10V_AV_1 (MTVSRBM, "mtvsrbm", CONST, vec_mtvsr_v16qi)
+BU_P10V_AV_1 (MTVSRHM, "mtvsrhm", CONST, vec_mtvsr_v8hi)
+BU_P10V_AV_1 (MTVSRWM, "mtvsrwm", CONST, vec_mtvsr_v4si)
+BU_P10V_AV_1 (MTVSRDM, "mtvsrdm", CONST, vec_mtvsr_v2di)
+BU_P10V_AV_1 (MTVSRQM, "mtvsrqm", CONST, vec_mtvsr_v1ti)
+BU_P10V_AV_2 (VCNTMBB, "cntmbb", CONST, vec_cntmb_v16qi)
+BU_P10V_AV_2 (VCNTMBH, "cntmbh", CONST, vec_cntmb_v8hi)
+BU_P10V_AV_2 (VCNTMBW, "cntmbw", CONST, vec_cntmb_v4si)
+BU_P10V_AV_2 (VCNTMBD, "cntmbd", CONST, vec_cntmb_v2di)
+BU_P10V_AV_1 (VEXPANDMB, "vexpandmb", CONST, vec_expand_v16qi)
+BU_P10V_AV_1 (VEXPANDMH, "vexpandmh", CONST, vec_expand_v8hi)
+BU_P10V_AV_1 (VEXPANDMW, "vexpandmw", CONST, vec_expand_v4si)
+BU_P10V_AV_1 (VEXPANDMD, "vexpandmd", CONST, vec_expand_v2di)
+BU_P10V_AV_1 (VEXPANDMQ, "vexpandmq", CONST, vec_expand_v1ti)
+BU_P10V_AV_1 (VEXTRACTMB, "vextractmb", CONST, vec_extract_v16qi)
+BU_P10V_AV_1 (VEXTRACTMH, "vextractmh", CONST, vec_extract_v8hi)
+BU_P10V_AV_1 (VEXTRACTMW, "vextractmw", CONST, vec_extract_v4si)
+BU_P10V_AV_1 (VEXTRACTMD, "vextractmd", CONST, vec_extract_v2di)
+BU_P10V_AV_1 (VEXTRACTMQ, "vextractmq", CONST, vec_extract_v1ti)
/* Overloaded vector builtins for ISA 3.1 (power10). */
BU_P10_OVERLOAD_2 (CLRL, "clrl")
@@ -2998,8 +3023,8 @@ BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS,
RS6000_BTC_MISC)
/* POWER10 MMA builtins. */
-BU_VSX_1 (XVCVBF16SP, "xvcvbf16sp", MISC, vsx_xvcvbf16sp)
-BU_VSX_1 (XVCVSPBF16, "xvcvspbf16", MISC, vsx_xvcvspbf16)
+BU_P10V_VSX_1 (XVCVBF16SP, "xvcvbf16sp", CONST, vsx_xvcvbf16sp)
+BU_P10V_VSX_1 (XVCVSPBF16, "xvcvspbf16", CONST, vsx_xvcvspbf16)
BU_MMA_1 (XXMFACC, "xxmfacc", QUAD, mma_xxmfacc)
BU_MMA_1 (XXMTACC, "xxmtacc", QUAD, mma_xxmtacc)
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 2fad3d94706..f5982907e90 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -1801,12 +1801,12 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
}
}
else if ((fcode == P10_BUILTIN_VEC_XXEVAL)
- || (fcode == P10_BUILTIN_VXXPERMX))
+ || (fcode == P10V_BUILTIN_VXXPERMX))
{
signed char op3_type;
/* Need to special case P10_BUILTIN_VEC_XXEVAL and
- P10_BUILTIN_VXXPERMX because they take 4 arguments and the
+ P10V_BUILTIN_VXXPERMX because they take 4 arguments and the
existing infrastructure only handles three. */
if (nargs != 4)
{
@@ -1821,7 +1821,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
{
if (fcode == P10_BUILTIN_VEC_XXEVAL)
op3_type = desc->op3;
- else /* P10_BUILTIN_VXXPERMX */
+ else /* P10V_BUILTIN_VXXPERMX */
op3_type = RS6000_BTI_V16QI;
if (rs6000_builtin_type_compatible (types[0], desc->op1)
diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
index 189497efb45..9cd43d7e468 100644
--- a/gcc/config/rs6000/rs6000-call.c
+++ b/gcc/config/rs6000/rs6000-call.c
@@ -5528,366 +5528,366 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
RS6000_BTI_INTSI, RS6000_BTI_INTSI },
/* Overloaded built-in functions for ISA3.1 (power10). */
- { P10_BUILTIN_VEC_CLRL, P10_BUILTIN_VCLRLB,
+ { P10_BUILTIN_VEC_CLRL, P10V_BUILTIN_VCLRLB,
RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 },
- { P10_BUILTIN_VEC_CLRL, P10_BUILTIN_VCLRLB,
+ { P10_BUILTIN_VEC_CLRL, P10V_BUILTIN_VCLRLB,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_UINTSI, 0 },
- { P10_BUILTIN_VEC_CLRR, P10_BUILTIN_VCLRRB,
+ { P10_BUILTIN_VEC_CLRR, P10V_BUILTIN_VCLRRB,
RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 },
- { P10_BUILTIN_VEC_CLRR, P10_BUILTIN_VCLRRB,
+ { P10_BUILTIN_VEC_CLRR, P10V_BUILTIN_VCLRRB,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_UINTSI, 0 },
- { P10_BUILTIN_VEC_GNB, P10_BUILTIN_VGNB, RS6000_BTI_unsigned_long_long,
+ { P10_BUILTIN_VEC_GNB, P10V_BUILTIN_VGNB, RS6000_BTI_unsigned_long_long,
RS6000_BTI_unsigned_V1TI, RS6000_BTI_UINTQI, 0 },
- { P10_BUILTIN_VEC_XXGENPCVM, P10_BUILTIN_XXGENPCVM_V2DI,
+ { P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 },
- { P10_BUILTIN_VEC_XXGENPCVM, P10_BUILTIN_XXGENPCVM_V4SI,
+ { P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
- { P10_BUILTIN_VEC_XXGENPCVM, P10_BUILTIN_XXGENPCVM_V8HI,
+ { P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
- { P10_BUILTIN_VEC_XXGENPCVM, P10_BUILTIN_XXGENPCVM_V16QI,
+ { P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_INTSI, 0 },
/* The overloaded XXEVAL definitions are handled specially because the
fourth unsigned char operand is not encoded in this table. */
- { P10_BUILTIN_VEC_XXEVAL, P10_BUILTIN_XXEVAL,
+ { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
- { P10_BUILTIN_VEC_XXEVAL, P10_BUILTIN_XXEVAL,
+ { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
- { P10_BUILTIN_VEC_XXEVAL, P10_BUILTIN_XXEVAL,
+ { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
- { P10_BUILTIN_VEC_XXEVAL, P10_BUILTIN_XXEVAL,
+ { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
- { P10_BUILTIN_VEC_XXEVAL, P10_BUILTIN_XXEVAL,
+ { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
/* The overloaded XXPERMX definitions are handled specially because the
fourth unsigned char operand is not encoded in this table. */
- { P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
+ { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI,
RS6000_BTI_unsigned_V16QI },
- { P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
+ { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
- { P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
+ { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI,
RS6000_BTI_unsigned_V16QI },
- { P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
+ { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI },
- { P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
+ { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI,
RS6000_BTI_unsigned_V16QI },
- { P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
+ { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI },
- { P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
+ { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI,
RS6000_BTI_unsigned_V16QI },
- { P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
+ { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI },
- { P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
+ { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF,
RS6000_BTI_unsigned_V16QI },
- { P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
+ { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF,
RS6000_BTI_unsigned_V16QI },
- { P10_BUILTIN_VEC_EXTRACTL, P10_BUILTIN_VEXTRACTBL,
+ { P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTBL,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_EXTRACTL, P10_BUILTIN_VEXTRACTHL,
+ { P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTHL,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_EXTRACTL, P10_BUILTIN_VEXTRACTWL,
+ { P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTWL,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_EXTRACTL, P10_BUILTIN_VEXTRACTDL,
+ { P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTDL,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_INSERTL, P10_BUILTIN_VINSERTGPRBL,
+ { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRBL,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI },
- { P10_BUILTIN_VEC_INSERTL, P10_BUILTIN_VINSERTGPRHL,
+ { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRHL,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTHI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTSI },
- { P10_BUILTIN_VEC_INSERTL, P10_BUILTIN_VINSERTGPRWL,
+ { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRWL,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI },
- { P10_BUILTIN_VEC_INSERTL, P10_BUILTIN_VINSERTGPRDL,
+ { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRDL,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTDI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTSI },
- { P10_BUILTIN_VEC_INSERTL, P10_BUILTIN_VINSERTVPRBL,
+ { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTVPRBL,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_INSERTL, P10_BUILTIN_VINSERTVPRHL,
+ { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTVPRHL,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_INSERTL, P10_BUILTIN_VINSERTVPRWL,
+ { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTVPRWL,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_EXTRACTH, P10_BUILTIN_VEXTRACTBR,
+ { P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTBR,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_EXTRACTH, P10_BUILTIN_VEXTRACTHR,
+ { P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTHR,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_EXTRACTH, P10_BUILTIN_VEXTRACTWR,
+ { P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTWR,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_EXTRACTH, P10_BUILTIN_VEXTRACTDR,
+ { P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTDR,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_INSERTH, P10_BUILTIN_VINSERTGPRBR,
+ { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRBR,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI },
- { P10_BUILTIN_VEC_INSERTH, P10_BUILTIN_VINSERTGPRHR,
+ { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRHR,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTHI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTSI },
- { P10_BUILTIN_VEC_INSERTH, P10_BUILTIN_VINSERTGPRWR,
+ { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRWR,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI },
- { P10_BUILTIN_VEC_INSERTH, P10_BUILTIN_VINSERTGPRDR,
+ { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRDR,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTDI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTSI },
- { P10_BUILTIN_VEC_INSERTH, P10_BUILTIN_VINSERTVPRBR,
+ { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTVPRBR,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_INSERTH, P10_BUILTIN_VINSERTVPRHR,
+ { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTVPRHR,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_INSERTH, P10_BUILTIN_VINSERTVPRWR,
+ { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTVPRWR,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_REPLACE_ELT, P10_BUILTIN_VREPLACE_ELT_UV4SI,
+ { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_UV4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_UINTSI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_REPLACE_ELT, P10_BUILTIN_VREPLACE_ELT_V4SI,
+ { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V4SI,
RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTQI },
- { P10_BUILTIN_VEC_REPLACE_ELT, P10_BUILTIN_VREPLACE_ELT_V4SF,
+ { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V4SF,
RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_float, RS6000_BTI_INTQI },
- { P10_BUILTIN_VEC_REPLACE_ELT, P10_BUILTIN_VREPLACE_ELT_UV2DI,
+ { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_UV2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_UINTDI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_REPLACE_ELT, P10_BUILTIN_VREPLACE_ELT_V2DI,
+ { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V2DI,
RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTDI, RS6000_BTI_INTQI },
- { P10_BUILTIN_VEC_REPLACE_ELT, P10_BUILTIN_VREPLACE_ELT_V2DF,
+ { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V2DF,
RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_double, RS6000_BTI_INTQI },
- { P10_BUILTIN_VEC_REPLACE_UN, P10_BUILTIN_VREPLACE_UN_UV4SI,
+ { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_UV4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_UINTSI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_REPLACE_UN, P10_BUILTIN_VREPLACE_UN_V4SI,
+ { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V4SI,
RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTQI },
- { P10_BUILTIN_VEC_REPLACE_UN, P10_BUILTIN_VREPLACE_UN_V4SF,
+ { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V4SF,
RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_float, RS6000_BTI_INTQI },
- { P10_BUILTIN_VEC_REPLACE_UN, P10_BUILTIN_VREPLACE_UN_UV2DI,
+ { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_UV2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_UINTDI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_REPLACE_UN, P10_BUILTIN_VREPLACE_UN_V2DI,
+ { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V2DI,
RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTDI, RS6000_BTI_INTQI },
- { P10_BUILTIN_VEC_REPLACE_UN, P10_BUILTIN_VREPLACE_UN_V2DF,
+ { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V2DF,
RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_double, RS6000_BTI_INTQI },
- { P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V16QI,
+ { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V16QI,
RS6000_BTI_V16QI, RS6000_BTI_V16QI,
RS6000_BTI_V16QI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V16QI,
+ { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V8HI,
+ { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V8HI,
RS6000_BTI_V8HI, RS6000_BTI_V8HI,
RS6000_BTI_V8HI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V8HI,
+ { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V4SI,
+ { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V4SI,
RS6000_BTI_V4SI, RS6000_BTI_V4SI,
RS6000_BTI_V4SI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V4SI,
+ { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V2DI,
+ { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V2DI,
RS6000_BTI_V2DI, RS6000_BTI_V2DI,
RS6000_BTI_V2DI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V2DI,
+ { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_XXSPLTIW, P10_BUILTIN_VXXSPLTIW_V4SI,
+ { P10_BUILTIN_VEC_XXSPLTIW, P10V_BUILTIN_VXXSPLTIW_V4SI,
RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0, 0 },
- { P10_BUILTIN_VEC_XXSPLTIW, P10_BUILTIN_VXXSPLTIW_V4SF,
+ { P10_BUILTIN_VEC_XXSPLTIW, P10V_BUILTIN_VXXSPLTIW_V4SF,
RS6000_BTI_V4SF, RS6000_BTI_float, 0, 0 },
- { P10_BUILTIN_VEC_XXSPLTID, P10_BUILTIN_VXXSPLTID,
+ { P10_BUILTIN_VEC_XXSPLTID, P10V_BUILTIN_VXXSPLTID,
RS6000_BTI_V2DF, RS6000_BTI_float, 0, 0 },
- { P10_BUILTIN_VEC_XXSPLTI32DX, P10_BUILTIN_VXXSPLTI32DX_V4SI,
+ { P10_BUILTIN_VEC_XXSPLTI32DX, P10V_BUILTIN_VXXSPLTI32DX_V4SI,
RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_UINTQI, RS6000_BTI_INTSI },
- { P10_BUILTIN_VEC_XXSPLTI32DX, P10_BUILTIN_VXXSPLTI32DX_V4SI,
+ { P10_BUILTIN_VEC_XXSPLTI32DX, P10V_BUILTIN_VXXSPLTI32DX_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI,
RS6000_BTI_UINTSI },
- { P10_BUILTIN_VEC_XXSPLTI32DX, P10_BUILTIN_VXXSPLTI32DX_V4SF,
+ { P10_BUILTIN_VEC_XXSPLTI32DX, P10V_BUILTIN_VXXSPLTI32DX_V4SF,
RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_UINTQI, RS6000_BTI_float },
- { P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V16QI,
+ { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V16QI,
RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI,
RS6000_BTI_unsigned_V16QI },
- { P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V16QI,
+ { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
- { P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V8HI,
+ { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V8HI,
RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI,
RS6000_BTI_unsigned_V8HI },
- { P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V8HI,
+ { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
- { P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V4SI,
+ { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V4SI,
RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI,
RS6000_BTI_unsigned_V4SI },
- { P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V4SI,
+ { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
- { P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V2DI,
+ { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V2DI,
RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI,
RS6000_BTI_unsigned_V2DI },
- { P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V2DI,
+ { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
- { P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V4SF,
+ { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V4SF,
RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF,
RS6000_BTI_unsigned_V4SI },
- { P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V2DF,
+ { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V2DF,
RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF,
RS6000_BTI_unsigned_V2DI },
- { P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V16QI,
+ { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V16QI,
RS6000_BTI_V16QI, RS6000_BTI_V16QI,
RS6000_BTI_V16QI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V16QI,
+ { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V8HI,
+ { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V8HI,
RS6000_BTI_V8HI, RS6000_BTI_V8HI,
RS6000_BTI_V8HI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V8HI,
+ { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V4SI,
+ { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V4SI,
RS6000_BTI_V4SI, RS6000_BTI_V4SI,
RS6000_BTI_V4SI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V4SI,
+ { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V2DI,
+ { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V2DI,
RS6000_BTI_V2DI, RS6000_BTI_V2DI,
RS6000_BTI_V2DI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V2DI,
+ { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI },
- { P10_BUILTIN_VEC_VSTRIL, P10_BUILTIN_VSTRIBL,
+ { P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIBL,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
- { P10_BUILTIN_VEC_VSTRIL, P10_BUILTIN_VSTRIBL,
+ { P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIBL,
RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
- { P10_BUILTIN_VEC_VSTRIL, P10_BUILTIN_VSTRIHL,
+ { P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIHL,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
- { P10_BUILTIN_VEC_VSTRIL, P10_BUILTIN_VSTRIHL,
+ { P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIHL,
RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
- { P10_BUILTIN_VEC_VSTRIL_P, P10_BUILTIN_VSTRIBL_P,
+ { P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIBL_P,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
- { P10_BUILTIN_VEC_VSTRIL_P, P10_BUILTIN_VSTRIBL_P,
+ { P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIBL_P,
RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
- { P10_BUILTIN_VEC_VSTRIL_P, P10_BUILTIN_VSTRIHL_P,
+ { P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIHL_P,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 },
- { P10_BUILTIN_VEC_VSTRIL_P, P10_BUILTIN_VSTRIHL_P,
+ { P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIHL_P,
RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
- { P10_BUILTIN_VEC_VSTRIR, P10_BUILTIN_VSTRIBR,
+ { P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIBR,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
- { P10_BUILTIN_VEC_VSTRIR, P10_BUILTIN_VSTRIBR,
+ { P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIBR,
RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
- { P10_BUILTIN_VEC_VSTRIR, P10_BUILTIN_VSTRIHR,
+ { P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIHR,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
- { P10_BUILTIN_VEC_VSTRIR, P10_BUILTIN_VSTRIHR,
+ { P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIHR,
RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
- { P10_BUILTIN_VEC_VSTRIR_P, P10_BUILTIN_VSTRIBR_P,
+ { P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIBR_P,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
- { P10_BUILTIN_VEC_VSTRIR_P, P10_BUILTIN_VSTRIBR_P,
+ { P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIBR_P,
RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
- { P10_BUILTIN_VEC_VSTRIR_P, P10_BUILTIN_VSTRIHR_P,
+ { P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIHR_P,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 },
- { P10_BUILTIN_VEC_VSTRIR_P, P10_BUILTIN_VSTRIHR_P,
+ { P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIHR_P,
RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
- { P10_BUILTIN_VEC_MTVSRBM, P10_BUILTIN_MTVSRBM,
+ { P10_BUILTIN_VEC_MTVSRBM, P10V_BUILTIN_MTVSRBM,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI, 0, 0 },
- { P10_BUILTIN_VEC_MTVSRHM, P10_BUILTIN_MTVSRHM,
+ { P10_BUILTIN_VEC_MTVSRHM, P10V_BUILTIN_MTVSRHM,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTDI, 0, 0 },
- { P10_BUILTIN_VEC_MTVSRWM, P10_BUILTIN_MTVSRWM,
+ { P10_BUILTIN_VEC_MTVSRWM, P10V_BUILTIN_MTVSRWM,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTDI, 0, 0 },
- { P10_BUILTIN_VEC_MTVSRDM, P10_BUILTIN_MTVSRDM,
+ { P10_BUILTIN_VEC_MTVSRDM, P10V_BUILTIN_MTVSRDM,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTDI, 0, 0 },
- { P10_BUILTIN_VEC_MTVSRQM, P10_BUILTIN_MTVSRQM,
+ { P10_BUILTIN_VEC_MTVSRQM, P10V_BUILTIN_MTVSRQM,
RS6000_BTI_unsigned_V1TI, RS6000_BTI_UINTDI, 0, 0 },
- { P10_BUILTIN_VEC_VCNTM, P10_BUILTIN_VCNTMBB,
+ { P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBB,
RS6000_BTI_unsigned_long_long,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI, 0 },
- { P10_BUILTIN_VEC_VCNTM, P10_BUILTIN_VCNTMBH,
+ { P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBH,
RS6000_BTI_unsigned_long_long,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI, 0 },
- { P10_BUILTIN_VEC_VCNTM, P10_BUILTIN_VCNTMBW,
+ { P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBW,
RS6000_BTI_unsigned_long_long,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI, 0 },
- { P10_BUILTIN_VEC_VCNTM, P10_BUILTIN_VCNTMBD,
+ { P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBD,
RS6000_BTI_unsigned_long_long,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI, 0 },
- { P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMB,
+ { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMB,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
- { P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMH,
+ { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMH,
RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
- { P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMW,
+ { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMW,
RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
- { P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMD,
+ { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMD,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
- { P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMQ,
+ { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMQ,
RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
- { P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMB,
+ { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMB,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
- { P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMH,
+ { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMH,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 },
- { P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMW,
+ { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMW,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, 0, 0 },
- { P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMD,
+ { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMD,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, 0, 0 },
- { P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMQ,
+ { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMQ,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, 0, 0 },
- { P10_BUILTIN_VEC_XVTLSBB_ZEROS, P10_BUILTIN_XVTLSBB_ZEROS,
+ { P10_BUILTIN_VEC_XVTLSBB_ZEROS, P10V_BUILTIN_XVTLSBB_ZEROS,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
- { P10_BUILTIN_VEC_XVTLSBB_ONES, P10_BUILTIN_XVTLSBB_ONES,
+ { P10_BUILTIN_VEC_XVTLSBB_ONES, P10V_BUILTIN_XVTLSBB_ONES,
RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
{ RS6000_BUILTIN_NONE, RS6000_BUILTIN_NONE, 0, 0, 0, 0 }
@@ -13937,7 +13937,7 @@ builtin_quaternary_function_type (machine_mode mode_ret,
switch (builtin) {
- case P10_BUILTIN_XXEVAL:
+ case P10V_BUILTIN_XXEVAL:
gcc_assert ((mode_ret == V2DImode)
&& (mode_arg0 == V2DImode)
&& (mode_arg1 == V2DImode)
@@ -13946,7 +13946,7 @@ builtin_quaternary_function_type (machine_mode mode_ret,
function_type = xxeval_type;
break;
- case P10_BUILTIN_VXXPERMX:
+ case P10V_BUILTIN_VXXPERMX:
gcc_assert ((mode_ret == V2DImode)
&& (mode_arg0 == V2DImode)
&& (mode_arg1 == V2DImode)
@@ -14004,22 +14004,22 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
case P8V_BUILTIN_VGBBD:
case MISC_BUILTIN_CDTBCD:
case MISC_BUILTIN_CBCDTD:
- case VSX_BUILTIN_XVCVSPBF16:
- case VSX_BUILTIN_XVCVBF16SP:
- case P10_BUILTIN_MTVSRBM:
- case P10_BUILTIN_MTVSRHM:
- case P10_BUILTIN_MTVSRWM:
- case P10_BUILTIN_MTVSRDM:
- case P10_BUILTIN_MTVSRQM:
- case P10_BUILTIN_VCNTMBB:
- case P10_BUILTIN_VCNTMBH:
- case P10_BUILTIN_VCNTMBW:
- case P10_BUILTIN_VCNTMBD:
- case P10_BUILTIN_VEXPANDMB:
- case P10_BUILTIN_VEXPANDMH:
- case P10_BUILTIN_VEXPANDMW:
- case P10_BUILTIN_VEXPANDMD:
- case P10_BUILTIN_VEXPANDMQ:
+ case P10V_BUILTIN_XVCVSPBF16:
+ case P10V_BUILTIN_XVCVBF16SP:
+ case P10V_BUILTIN_MTVSRBM:
+ case P10V_BUILTIN_MTVSRHM:
+ case P10V_BUILTIN_MTVSRWM:
+ case P10V_BUILTIN_MTVSRDM:
+ case P10V_BUILTIN_MTVSRQM:
+ case P10V_BUILTIN_VCNTMBB:
+ case P10V_BUILTIN_VCNTMBH:
+ case P10V_BUILTIN_VCNTMBW:
+ case P10V_BUILTIN_VCNTMBD:
+ case P10V_BUILTIN_VEXPANDMB:
+ case P10V_BUILTIN_VEXPANDMH:
+ case P10V_BUILTIN_VEXPANDMW:
+ case P10V_BUILTIN_VEXPANDMD:
+ case P10V_BUILTIN_VEXPANDMQ:
h.uns_p[0] = 1;
h.uns_p[1] = 1;
break;
@@ -14091,16 +14091,16 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
case P8V_BUILTIN_ORC_V4SI_UNS:
case P8V_BUILTIN_ORC_V2DI_UNS:
case P8V_BUILTIN_ORC_V1TI_UNS:
- case P10_BUILTIN_VCFUGED:
- case P10_BUILTIN_VCLZDM:
- case P10_BUILTIN_VCTZDM:
- case P10_BUILTIN_VGNB:
- case P10_BUILTIN_VPDEPD:
- case P10_BUILTIN_VPEXTD:
- case P10_BUILTIN_XXGENPCVM_V16QI:
- case P10_BUILTIN_XXGENPCVM_V8HI:
- case P10_BUILTIN_XXGENPCVM_V4SI:
- case P10_BUILTIN_XXGENPCVM_V2DI:
+ case P10V_BUILTIN_VCFUGED:
+ case P10V_BUILTIN_VCLZDM:
+ case P10V_BUILTIN_VCTZDM:
+ case P10V_BUILTIN_VGNB:
+ case P10V_BUILTIN_VPDEPD:
+ case P10V_BUILTIN_VPEXTD:
+ case P10V_BUILTIN_XXGENPCVM_V16QI:
+ case P10V_BUILTIN_XXGENPCVM_V8HI:
+ case P10V_BUILTIN_XXGENPCVM_V4SI:
+ case P10V_BUILTIN_XXGENPCVM_V2DI:
h.uns_p[0] = 1;
h.uns_p[1] = 1;
h.uns_p[2] = 1;
@@ -14131,29 +14131,29 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
case CRYPTO_BUILTIN_VSHASIGMAW:
case CRYPTO_BUILTIN_VSHASIGMAD:
case CRYPTO_BUILTIN_VSHASIGMA:
- case P10_BUILTIN_VEXTRACTBL:
- case P10_BUILTIN_VEXTRACTHL:
- case P10_BUILTIN_VEXTRACTWL:
- case P10_BUILTIN_VEXTRACTDL:
- case P10_BUILTIN_VEXTRACTBR:
- case P10_BUILTIN_VEXTRACTHR:
- case P10_BUILTIN_VEXTRACTWR:
- case P10_BUILTIN_VEXTRACTDR:
- case P10_BUILTIN_VINSERTGPRBL:
- case P10_BUILTIN_VINSERTGPRHL:
- case P10_BUILTIN_VINSERTGPRWL:
- case P10_BUILTIN_VINSERTGPRDL:
- case P10_BUILTIN_VINSERTVPRBL:
- case P10_BUILTIN_VINSERTVPRHL:
- case P10_BUILTIN_VINSERTVPRWL:
- case P10_BUILTIN_VREPLACE_ELT_UV4SI:
- case P10_BUILTIN_VREPLACE_ELT_UV2DI:
- case P10_BUILTIN_VREPLACE_UN_UV4SI:
- case P10_BUILTIN_VREPLACE_UN_UV2DI:
- case P10_BUILTIN_VXXBLEND_V16QI:
- case P10_BUILTIN_VXXBLEND_V8HI:
- case P10_BUILTIN_VXXBLEND_V4SI:
- case P10_BUILTIN_VXXBLEND_V2DI:
+ case P10V_BUILTIN_VEXTRACTBL:
+ case P10V_BUILTIN_VEXTRACTHL:
+ case P10V_BUILTIN_VEXTRACTWL:
+ case P10V_BUILTIN_VEXTRACTDL:
+ case P10V_BUILTIN_VEXTRACTBR:
+ case P10V_BUILTIN_VEXTRACTHR:
+ case P10V_BUILTIN_VEXTRACTWR:
+ case P10V_BUILTIN_VEXTRACTDR:
+ case P10V_BUILTIN_VINSERTGPRBL:
+ case P10V_BUILTIN_VINSERTGPRHL:
+ case P10V_BUILTIN_VINSERTGPRWL:
+ case P10V_BUILTIN_VINSERTGPRDL:
+ case P10V_BUILTIN_VINSERTVPRBL:
+ case P10V_BUILTIN_VINSERTVPRHL:
+ case P10V_BUILTIN_VINSERTVPRWL:
+ case P10V_BUILTIN_VREPLACE_ELT_UV4SI:
+ case P10V_BUILTIN_VREPLACE_ELT_UV2DI:
+ case P10V_BUILTIN_VREPLACE_UN_UV4SI:
+ case P10V_BUILTIN_VREPLACE_UN_UV2DI:
+ case P10V_BUILTIN_VXXBLEND_V16QI:
+ case P10V_BUILTIN_VXXBLEND_V8HI:
+ case P10V_BUILTIN_VXXBLEND_V4SI:
+ case P10V_BUILTIN_VXXBLEND_V2DI:
h.uns_p[0] = 1;
h.uns_p[1] = 1;
h.uns_p[2] = 1;
@@ -14221,8 +14221,8 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
case ALTIVEC_BUILTIN_VSRW:
case P8V_BUILTIN_VSRD:
/* Vector splat immediate insert */
- case P10_BUILTIN_VXXSPLTI32DX_V4SI:
- case P10_BUILTIN_VXXSPLTI32DX_V4SF:
+ case P10V_BUILTIN_VXXSPLTI32DX_V4SI:
+ case P10V_BUILTIN_VXXSPLTI32DX_V4SF:
h.uns_p[2] = 1;
break;
--
2.25.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
2020-08-13 16:12 [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions Carl Love
@ 2020-08-13 18:38 ` Bill Schmidt
2020-08-13 19:24 ` Carl Love
2020-08-14 21:33 ` Segher Boessenkool
1 sibling, 1 reply; 20+ messages in thread
From: Bill Schmidt @ 2020-08-13 18:38 UTC (permalink / raw)
To: Carl Love, Segher Boessenkool, dje.gcc, gcc-patches, Will Schmidt
Cc: Bill Schmidt, cel, Peter Bergner
On 8/13/20 11:12 AM, Carl Love wrote:
> GCC maintainers:
>
> The macro expansion for the bfloat convert intrinsics XVCVBF16SP and
> XVCVSPBF16 need to be restricted to P10.
>
> The macro expansions BU_P10V_0, BU_P10V_1, BU_P10V_2, BU_P10V_3 expand
> the name field as "__builtin_altivec_". These macro expansions are
> being used for both VSX and Altivec instructions. There needs to be
> separate expansions for VSX with the name field "__builtin_vsx_" and
> for Altivec with the name field "__builtin_altivec_".
>
> The following patch creates new macro expansions BU_P10V_VSX_# and
> BU_P10V_AV_# for the VSX and Altivec instructions respectively. The
> new names are consistent with the P8 and P9 naming convention for the
> VSX and Altivec instructions.
>
> The macro expansion for XVCVBF16SP and XVCVSPBF16 is changed from
> BU_VSX_1 to BU_P10V_VSX_1 to restrict it to P10 and beyond. Also MISC
> is changed to CONST in the macro expansion call.
>
> The side effect of creating the macro expansions for VSX and Altivec is
> it changes all of the expanded names. The patch fixes all the uses of
> the expanded names as needed for the new VSX and Altivec macros.
>
> The patch has been run on
>
> powerpc64le-unknown-linux-gnu (Power 8 LE)
> powerpc64le-unknown-linux-gnu (Power 9 LE)
>
> with no regressions.
>
> Please let me know if the patch is acceptable for trunk.
Hi Carl,
Thanks for cleaning up the consistency issue. The new names and related
adjustments LGTM.
Are there no affected test cases that need adjusting? That surprises
me. For example, didn't __builtin_altivec_xxeval become
__builtin_vsx_xxeval as a result of this change? Does that not appear
in any test cases?
Thanks,
Bill
>
> Carl Love
>
> -----------------------------------------------------------------
> [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
>
> gcc/ChangeLog
>
> 2020-08-12 Carl Love <cel@us.ibm.com>
> * config/rs6000/rs6000-builtin.def (BU_P10V_0, BU_P10V_1,
> BU_P10V_2, BU_P10V_3): Rename BU_P10V_VSX_0, BU_P10V_VSX_1,
> BU_P10V_VSX_2, BU_P10V_VSX_3 respectively.
> (BU_P10V_4): Remove.
> (BU_P10V_AV_0, BU_P10V_AV_1, BU_P10V_AV_2, BU_P10V_AV_3, BU_P10V_AV_4):
> New definitions for Power 10 Altivec macros.
> (VSTRIBR, VSTRIHR, VSTRIBL, VSTRIHL, VSTRIBR_P, VSTRIHR_P,
> VSTRIBL_P, VSTRIHL_P, MTVSRBM, MTVSRHM, MTVSRWM, MTVSRDM, MTVSRQM,
> VEXPANDMB, VEXPANDMH, VEXPANDMW, VEXPANDMD, VEXPANDMQ, VEXTRACTMB,
> VEXTRACTMH, VEXTRACTMW, VEXTRACTMD, VEXTRACTMQ): Replace macro
> expansion BU_P10V_1 with BU_P10V_AV_1.
> (VCLRLB, VCLRRB, VCFUGED, VCLZDM, VCTZDM, VPDEPD, VPEXTD, VGNB,
> VCNTMBB, VCNTMBH, VCNTMBW, VCNTMBD): Replace macro expansion
> BU_P10V_2 with BU_P10V_AV_2.
> (VEXTRACTBL, VEXTRACTHL, VEXTRACTWL, VEXTRACTDL, VEXTRACTBR, VEXTRACTHR,
> VEXTRACTWR, VEXTRACTDR, VINSERTGPRBL, VINSERTGPRHL, VINSERTGPRWL,
> VINSERTGPRDL, VINSERTVPRBL, VINSERTVPRHL, VINSERTVPRWL, VINSERTGPRBR,
> VINSERTGPRHR, VINSERTGPRWR, VINSERTGPRDR, VINSERTVPRBR, VINSERTVPRHR,
> VINSERTVPRWR, VREPLACE_ELT_V4SI, VREPLACE_ELT_UV4SI, VREPLACE_ELT_V2DF,
> VREPLACE_ELT_V4SF, VREPLACE_ELT_V2DI, VREPLACE_ELT_UV2DI, VREPLACE_UN_V4SI,
> VREPLACE_UN_UV4SI, VREPLACE_UN_V4SF, VREPLACE_UN_V2DI, VREPLACE_UN_UV2DI,
> VREPLACE_UN_V2DF, VSLDB_V16QI, VSLDB_V8HI, VSLDB_V4SI, VSLDB_V2DI,
> VSRDB_V16QI, VSRDB_V8HI, VSRDB_V4SI, VSRDB_V2DI): Replace macro expansion
> BU_P10V_3 with BU_P10V_AV_3.
> (VXXSPLTIW_V4SI, VXXSPLTIW_V4SF, VXXSPLTID): Replace macro expansion
> BU_P10V_1 with BU_P10V_AV_1.
> (XXGENPCVM_V16QI, XXGENPCVM_V8HI, XXGENPCVM_V4SI, XXGENPCVM_V2DI):
> Replace macro expansion BU_P10V_2 with BU_P10V_VSX_2.
> (VXXSPLTI32DX_V4SI, VXXSPLTI32DX_V4SF, VXXBLEND_V16QI, VXXBLEND_V8HI,
> VXXBLEND_V4SI, VXXBLEND_V2DI, VXXBLEND_V4SF, VXXBLEND_V2DF): Replace macor
> expansion BU_P10V_3 with BU_P10V_VSX_3.
> (XXEVAL, VXXPERMX): Replace macro expansion BU_P10V_4 with BU_P10V_VSX_4.
> (XVCVBF16SP, XVCVSPBF16): Replace macro expansion BU_VSX_1 with
> BU_P10V_VSX_1. Also change MISC to CONST.
> * config/rs6000/rs6000-c.c: (P10_BUILTIN_VXXPERMX): Replace with
> P10V_BUILTIN_VXXPERMX.
> (P10_BUILTIN_VCLRLB, P10_BUILTIN_VCLRLB, P10_BUILTIN_VCLRRB,
> P10_BUILTIN_VGNB, P10_BUILTIN_XXEVAL, P10_BUILTIN_VXXPERMX,
> P10_BUILTIN_VEXTRACTBL, P10_BUILTIN_VEXTRACTHL, P10_BUILTIN_VEXTRACTWL,
> P10_BUILTIN_VEXTRACTDL, P10_BUILTIN_VINSERTGPRHL,
> P10_BUILTIN_VINSERTGPRWL, P10_BUILTIN_VINSERTGPRDL,
> P10_BUILTIN_VINSERTVPRBL, P10_BUILTIN_VINSERTVPRHL,
> P10_BUILTIN_VEXTRACTBR, P10_BUILTIN_VEXTRACTHR,
> P10_BUILTIN_VEXTRACTWR, P10_BUILTIN_VEXTRACTDR,
> P10_BUILTIN_VINSERTGPRBR, P10_BUILTIN_VINSERTGPRHR,
> P10_BUILTIN_VINSERTGPRWR, P10_BUILTIN_VINSERTGPRDR,
> P10_BUILTIN_VINSERTVPRBR, P10_BUILTIN_VINSERTVPRHR,
> P10_BUILTIN_VINSERTVPRWR, P10_BUILTIN_VREPLACE_ELT_UV4SI,
> P10_BUILTIN_VREPLACE_ELT_V4SI, P10_BUILTIN_VREPLACE_ELT_UV2DI,
> P10_BUILTIN_VREPLACE_ELT_V2DI, P10_BUILTIN_VREPLACE_ELT_V2DF,
> P10_BUILTIN_VREPLACE_UN_UV4SI, P10_BUILTIN_VREPLACE_UN_V4SI,
> P10_BUILTIN_VREPLACE_UN_V4SF, P10_BUILTIN_VREPLACE_UN_UV2DI,
> P10_BUILTIN_VREPLACE_UN_V2DI, P10_BUILTIN_VREPLACE_UN_V2DF,
> P10_BUILTIN_VSLDB_V16QI, P10_BUILTIN_VSLDB_V16QI,
> P10_BUILTIN_VSLDB_V8HI, P10_BUILTIN_VSLDB_V4SI,
> P10_BUILTIN_VSLDB_V2DI, P10_BUILTIN_VXXSPLTIW_V4SI,
> P10_BUILTIN_VXXSPLTIW_V4SF, P10_BUILTIN_VXXSPLTID,
> P10_BUILTIN_VXXSPLTI32DX_V4SI, P10_BUILTIN_VXXSPLTI32DX_V4SF,
> P10_BUILTIN_VXXBLEND_V16QI, P10_BUILTIN_VXXBLEND_V8HI,
> P10_BUILTIN_VXXBLEND_V4SI, P10_BUILTIN_VXXBLEND_V2DI,
> P10_BUILTIN_VXXBLEND_V4SF, P10_BUILTIN_VXXBLEND_V2DF,
> P10_BUILTIN_VSRDB_V16QI, P10_BUILTIN_VSRDB_V8HI,
> P10_BUILTIN_VSRDB_V4SI, P10_BUILTIN_VSRDB_V2DI,
> P10_BUILTIN_VSTRIBL, P10_BUILTIN_VSTRIHL,
> P10_BUILTIN_VSTRIBL_P, P10_BUILTIN_VSTRIHL_P,
> P10_BUILTIN_VSTRIBR, P10_BUILTIN_VSTRIHR,
> P10_BUILTIN_VSTRIBR_P, P10_BUILTIN_VSTRIHR_P,
> P10_BUILTIN_MTVSRBM, P10_BUILTIN_MTVSRHM,
> P10_BUILTIN_MTVSRWM, P10_BUILTIN_MTVSRDM,
> P10_BUILTIN_MTVSRQM, P10_BUILTIN_VCNTMBB,
> P10_BUILTIN_VCNTMBH, P10_BUILTIN_VCNTMBW,
> P10_BUILTIN_VCNTMBD, P10_BUILTIN_VEXPANDMB,
> P10_BUILTIN_VEXPANDMH, P10_BUILTIN_VEXPANDMW,
> P10_BUILTIN_VEXPANDMD, P10_BUILTIN_VEXPANDMQ,
> P10_BUILTIN_VEXTRACTMB, P10_BUILTIN_VEXTRACTMH,
> P10_BUILTIN_VEXTRACTMW, P10_BUILTIN_VEXTRACTMD,
> P10_BUILTIN_VEXTRACTMQ, P10_BUILTIN_XVTLSBB_ZEROS,
> P10_BUILTIN_XVTLSBB_ONES): Replace with
> P10V_BUILTIN_VCLRLB, P10V_BUILTIN_VCLRLB, P10V_BUILTIN_VCLRRB,
> P10V_BUILTIN_VGNB, P10V_BUILTIN_XXEVAL, P10V_BUILTIN_VXXPERMX,
> P10V_BUILTIN_VEXTRACTBL, P10V_BUILTIN_VEXTRACTHL, P10V_BUILTIN_VEXTRACTWL,
> P10V_BUILTIN_VEXTRACTDL, P10V_BUILTIN_VINSERTGPRHL,
> P10V_BUILTIN_VINSERTGPRWL, P10V_BUILTIN_VINSERTGPRDL,
> P10V_BUILTIN_VINSERTVPRBL,P10V_BUILTIN_VINSERTVPRHL,
> P10V_BUILTIN_VEXTRACTBR, P10V_BUILTIN_VEXTRACTHR
> P10V_BUILTIN_VEXTRACTWR, P10V_BUILTIN_VEXTRACTDR,
> P10V_BUILTIN_VINSERTGPRBR, P10V_BUILTIN_VINSERTGPRHR,
> P10V_BUILTIN_VINSERTGPRWR, P10V_BUILTIN_VINSERTGPRDR,
> P10V_BUILTIN_VINSERTVPRBR, P10V_BUILTIN_VINSERTVPRHR,
> P10V_BUILTIN_VINSERTVPRWR, P10V_BUILTIN_VREPLACE_ELT_UV4SI,
> P10V_BUILTIN_VREPLACE_ELT_V4SI, P10V_BUILTIN_VREPLACE_ELT_UV2DI,
> P10V_BUILTIN_VREPLACE_ELT_V2DI, P10V_BUILTIN_VREPLACE_ELT_V2DF,
> P10V_BUILTIN_VREPLACE_UN_UV4SI, P10V_BUILTIN_VREPLACE_UN_V4SI,
> P10V_BUILTIN_VREPLACE_UN_V4SF, P10V_BUILTIN_VREPLACE_UN_UV2DI,
> P10V_BUILTIN_VREPLACE_UN_V2DI, P10V_BUILTIN_VREPLACE_UN_V2DF,
> P10V_BUILTIN_VSLDB_V16QI, P10V_BUILTIN_VSLDB_V16QI,
> P10V_BUILTIN_VSLDB_V8HI, P10V_BUILTIN_VSLDB_V4SI,
> P10V_BUILTIN_VSLDB_V2DI, P10V_BUILTIN_VXXSPLTIW_V4SI,
> P10V_BUILTIN_VXXSPLTIW_V4SF, P10V_BUILTIN_VXXSPLTID,
> P10V_BUILTIN_VXXSPLTI32DX_V4SI, P10V_BUILTIN_VXXSPLTI32DX_V4SF,
> P10V_BUILTIN_VXXBLEND_V16QI, P10V_BUILTIN_VXXBLEND_V8HI,
> P10V_BUILTIN_VXXBLEND_V4SI, P10V_BUILTIN_VXXBLEND_V2DI,
> P10V_BUILTIN_VXXBLEND_V4SF, P10V_BUILTIN_VXXBLEND_V2DF,
> P10V_BUILTIN_VSRDB_V16QI, P10V_BUILTIN_VSRDB_V8HI,
> P10V_BUILTIN_VSRDB_V4SI, P10V_BUILTIN_VSRDB_V2DI,
> P10V_BUILTIN_VSTRIBL, P10V_BUILTIN_VSTRIHL,
> P10V_BUILTIN_VSTRIBL_P, P10V_BUILTIN_VSTRIHL_P,
> P10V_BUILTIN_VSTRIBR, P10V_BUILTIN_VSTRIHR,
> P10V_BUILTIN_VSTRIBR_P, P10V_BUILTIN_VSTRIHR_P,
> P10V_BUILTIN_MTVSRBM, P10V_BUILTIN_MTVSRHM,
> P10V_BUILTIN_MTVSRWM, P10V_BUILTIN_MTVSRDM,
> P10V_BUILTIN_MTVSRQM, P10V_BUILTIN_VCNTMBB,
> P10V_BUILTIN_VCNTMBH, P10V_BUILTIN_VCNTMBW,
> P10V_BUILTIN_VCNTMBD, P10V_BUILTIN_VEXPANDMB,
> P10V_BUILTIN_VEXPANDMH, P10V_BUILTIN_VEXPANDMW,
> P10V_BUILTIN_VEXPANDMD, P10V_BUILTIN_VEXPANDMQ,
> P10V_BUILTIN_VEXTRACTMB, P10V_BUILTIN_VEXTRACTMH,
> P10V_BUILTIN_VEXTRACTMW, P10V_BUILTIN_VEXTRACTMD,
> P10V_BUILTIN_VEXTRACTMQ, P10V_BUILTIN_XVTLSBB_ZEROS,
> P10V_BUILTIN_XVTLSBB_ONES respectively.
> * config/rs6000/rs6000-call.c: Ditto above, change P10_BUILTIN_name to
> P10V_BUILTIN_name.
> (P10_BUILTIN_XVCVSPBF16, P10_BUILTIN_XVCVBF16SP): Change to
> P10V_BUILTIN_XVCVSPBF16, P10V_BUILTIN_XVCVBF16SP respectively.
> ---
> gcc/config/rs6000/rs6000-builtin.def | 303 +++++++++++-----------
> gcc/config/rs6000/rs6000-c.c | 6 +-
> gcc/config/rs6000/rs6000-call.c | 360 +++++++++++++--------------
> 3 files changed, 347 insertions(+), 322 deletions(-)
>
> diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
> index f9f0fece549..97b16dc1079 100644
> --- a/gcc/config/rs6000/rs6000-builtin.def
> +++ b/gcc/config/rs6000/rs6000-builtin.def
> @@ -1019,55 +1019,46 @@
> | RS6000_BTC_BINARY), \
> CODE_FOR_ ## ICODE) /* ICODE */
>
> -/* For builtins for power10 vector instructions that are encoded as altivec
> - instructions, use __builtin_altivec_ as the builtin name. */
> +/* Power 10 VSX builtins */
>
> -#define BU_P10V_0(ENUM, NAME, ATTR, ICODE) \
> +#define BU_P10V_VSX_0(ENUM, NAME, ATTR, ICODE) \
> RS6000_BUILTIN_0 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
> - "__builtin_altivec_" NAME, /* NAME */ \
> + "__builtin_vsx_" NAME, /* NAME */ \
> RS6000_BTM_P10, /* MASK */ \
> (RS6000_BTC_ ## ATTR /* ATTR */ \
> | RS6000_BTC_SPECIAL), \
> CODE_FOR_ ## ICODE) /* ICODE */
>
> -#define BU_P10V_1(ENUM, NAME, ATTR, ICODE) \
> - RS6000_BUILTIN_1 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
> - "__builtin_altivec_" NAME, /* NAME */ \
> +#define BU_P10V_VSX_1(ENUM, NAME, ATTR, ICODE) \
> + RS6000_BUILTIN_1 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
> + "__builtin_vsx_" NAME, /* NAME */ \
> RS6000_BTM_P10, /* MASK */ \
> (RS6000_BTC_ ## ATTR /* ATTR */ \
> | RS6000_BTC_UNARY), \
> CODE_FOR_ ## ICODE) /* ICODE */
>
> -#define BU_P10V_2(ENUM, NAME, ATTR, ICODE) \
> - RS6000_BUILTIN_2 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
> - "__builtin_altivec_" NAME, /* NAME */ \
> +#define BU_P10V_VSX_2(ENUM, NAME, ATTR, ICODE) \
> + RS6000_BUILTIN_2 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
> + "__builtin_vsx_" NAME, /* NAME */ \
> RS6000_BTM_P10, /* MASK */ \
> (RS6000_BTC_ ## ATTR /* ATTR */ \
> | RS6000_BTC_BINARY), \
> CODE_FOR_ ## ICODE) /* ICODE */
>
> -#define BU_P10V_3(ENUM, NAME, ATTR, ICODE) \
> - RS6000_BUILTIN_3 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
> - "__builtin_altivec_" NAME, /* NAME */ \
> +#define BU_P10V_VSX_3(ENUM, NAME, ATTR, ICODE) \
> + RS6000_BUILTIN_3 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
> + "__builtin_vsx_" NAME, /* NAME */ \
> RS6000_BTM_P10, /* MASK */ \
> (RS6000_BTC_ ## ATTR /* ATTR */ \
> | RS6000_BTC_TERNARY), \
> CODE_FOR_ ## ICODE) /* ICODE */
>
> -#define BU_P10V_4(ENUM, NAME, ATTR, ICODE) \
> - RS6000_BUILTIN_4 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
> - "__builtin_altivec_" NAME, /* NAME */ \
> - RS6000_BTM_P10, /* MASK */ \
> - (RS6000_BTC_ ## ATTR /* ATTR */ \
> - | RS6000_BTC_QUATERNARY), \
> - CODE_FOR_ ## ICODE) /* ICODE */
> -
> -#define BU_P10_VSX_1(ENUM, NAME, ATTR, ICODE) \
> - RS6000_BUILTIN_1 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
> +#define BU_P10V_VSX_4(ENUM, NAME, ATTR, ICODE) \
> + RS6000_BUILTIN_4 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
> "__builtin_vsx_" NAME, /* NAME */ \
> RS6000_BTM_P10, /* MASK */ \
> (RS6000_BTC_ ## ATTR /* ATTR */ \
> - | RS6000_BTC_UNARY), \
> + | RS6000_BTC_QUATERNARY), \
> CODE_FOR_ ## ICODE) /* ICODE */
>
> #define BU_P10_OVERLOAD_1(ENUM, NAME) \
> @@ -1154,6 +1145,40 @@
> CODE_FOR_ ## ICODE) /* ICODE */
> #endif
>
> +/* Power 10 Altivec builtins */
> +
> +#define BU_P10V_AV_0(ENUM, NAME, ATTR, ICODE) \
> + RS6000_BUILTIN_0 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
> + "__builtin_altivec_" NAME, /* NAME */ \
> + RS6000_BTM_P10, /* MASK */ \
> + (RS6000_BTC_ ## ATTR /* ATTR */ \
> + | RS6000_BTC_SPECIAL), \
> + CODE_FOR_ ## ICODE) /* ICODE */
> +
> +#define BU_P10V_AV_1(ENUM, NAME, ATTR, ICODE) \
> + RS6000_BUILTIN_1 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
> + "__builtin_altivec_" NAME, /* NAME */ \
> + RS6000_BTM_P10, /* MASK */ \
> + (RS6000_BTC_ ## ATTR /* ATTR */ \
> + | RS6000_BTC_UNARY), \
> + CODE_FOR_ ## ICODE) /* ICODE */
> +
> +#define BU_P10V_AV_2(ENUM, NAME, ATTR, ICODE) \
> + RS6000_BUILTIN_2 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
> + "__builtin_altivec_" NAME, /* NAME */ \
> + RS6000_BTM_P10, /* MASK */ \
> + (RS6000_BTC_ ## ATTR /* ATTR */ \
> + | RS6000_BTC_BINARY), \
> + CODE_FOR_ ## ICODE) /* ICODE */
> +
> +#define BU_P10V_AV_3(ENUM, NAME, ATTR, ICODE) \
> + RS6000_BUILTIN_3 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
> + "__builtin_altivec_" NAME, /* NAME */ \
> + RS6000_BTM_P10, /* MASK */ \
> + (RS6000_BTC_ ## ATTR /* ATTR */ \
> + | RS6000_BTC_TERNARY), \
> + CODE_FOR_ ## ICODE) /* ICODE */
> +
> \f
> /* Insure 0 is not a legitimate index. */
> BU_SPECIAL_X (RS6000_BUILTIN_NONE, NULL, 0, RS6000_BTC_MISC)
> @@ -2710,119 +2735,119 @@ BU_P10_MISC_2 (PDEPD, "pdepd", CONST, pdepd)
> BU_P10_MISC_2 (PEXTD, "pextd", CONST, pextd)
>
> /* Builtins for vector instructions added in ISA 3.1 (power10). */
> -BU_P10V_2 (VCLRLB, "vclrlb", CONST, vclrlb)
> -BU_P10V_2 (VCLRRB, "vclrrb", CONST, vclrrb)
> -BU_P10V_2 (VCFUGED, "vcfuged", CONST, vcfuged)
> -BU_P10V_2 (VCLZDM, "vclzdm", CONST, vclzdm)
> -BU_P10V_2 (VCTZDM, "vctzdm", CONST, vctzdm)
> -BU_P10V_2 (VPDEPD, "vpdepd", CONST, vpdepd)
> -BU_P10V_2 (VPEXTD, "vpextd", CONST, vpextd)
> -BU_P10V_2 (VGNB, "vgnb", CONST, vgnb)
> -BU_P10V_4 (XXEVAL, "xxeval", CONST, xxeval)
> -BU_P10V_2 (XXGENPCVM_V16QI, "xxgenpcvm_v16qi", CONST, xxgenpcvm_v16qi)
> -BU_P10V_2 (XXGENPCVM_V8HI, "xxgenpcvm_v8hi", CONST, xxgenpcvm_v8hi)
> -BU_P10V_2 (XXGENPCVM_V4SI, "xxgenpcvm_v4si", CONST, xxgenpcvm_v4si)
> -BU_P10V_2 (XXGENPCVM_V2DI, "xxgenpcvm_v2di", CONST, xxgenpcvm_v2di)
> -
> -BU_P10V_3 (VEXTRACTBL, "vextdubvlx", CONST, vextractlv16qi)
> -BU_P10V_3 (VEXTRACTHL, "vextduhvlx", CONST, vextractlv8hi)
> -BU_P10V_3 (VEXTRACTWL, "vextduwvlx", CONST, vextractlv4si)
> -BU_P10V_3 (VEXTRACTDL, "vextddvlx", CONST, vextractlv2di)
> -
> -BU_P10V_3 (VEXTRACTBR, "vextdubvhx", CONST, vextractrv16qi)
> -BU_P10V_3 (VEXTRACTHR, "vextduhvhx", CONST, vextractrv8hi)
> -BU_P10V_3 (VEXTRACTWR, "vextduwvhx", CONST, vextractrv4si)
> -BU_P10V_3 (VEXTRACTDR, "vextddvhx", CONST, vextractrv2di)
> -
> -BU_P10V_3 (VINSERTGPRBL, "vinsgubvlx", CONST, vinsertgl_v16qi)
> -BU_P10V_3 (VINSERTGPRHL, "vinsguhvlx", CONST, vinsertgl_v8hi)
> -BU_P10V_3 (VINSERTGPRWL, "vinsguwvlx", CONST, vinsertgl_v4si)
> -BU_P10V_3 (VINSERTGPRDL, "vinsgudvlx", CONST, vinsertgl_v2di)
> -BU_P10V_3 (VINSERTVPRBL, "vinsvubvlx", CONST, vinsertvl_v16qi)
> -BU_P10V_3 (VINSERTVPRHL, "vinsvuhvlx", CONST, vinsertvl_v8hi)
> -BU_P10V_3 (VINSERTVPRWL, "vinsvuwvlx", CONST, vinsertvl_v4si)
> -
> -BU_P10V_3 (VINSERTGPRBR, "vinsgubvrx", CONST, vinsertgr_v16qi)
> -BU_P10V_3 (VINSERTGPRHR, "vinsguhvrx", CONST, vinsertgr_v8hi)
> -BU_P10V_3 (VINSERTGPRWR, "vinsguwvrx", CONST, vinsertgr_v4si)
> -BU_P10V_3 (VINSERTGPRDR, "vinsgudvrx", CONST, vinsertgr_v2di)
> -BU_P10V_3 (VINSERTVPRBR, "vinsvubvrx", CONST, vinsertvr_v16qi)
> -BU_P10V_3 (VINSERTVPRHR, "vinsvuhvrx", CONST, vinsertvr_v8hi)
> -BU_P10V_3 (VINSERTVPRWR, "vinsvuwvrx", CONST, vinsertvr_v4si)
> -
> -BU_P10V_3 (VREPLACE_ELT_V4SI, "vreplace_v4si", CONST, vreplace_elt_v4si)
> -BU_P10V_3 (VREPLACE_ELT_UV4SI, "vreplace_uv4si", CONST, vreplace_elt_v4si)
> -BU_P10V_3 (VREPLACE_ELT_V4SF, "vreplace_v4sf", CONST, vreplace_elt_v4sf)
> -BU_P10V_3 (VREPLACE_ELT_V2DI, "vreplace_v2di", CONST, vreplace_elt_v2di)
> -BU_P10V_3 (VREPLACE_ELT_UV2DI, "vreplace_uv2di", CONST, vreplace_elt_v2di)
> -BU_P10V_3 (VREPLACE_ELT_V2DF, "vreplace_v2df", CONST, vreplace_elt_v2df)
> -
> -BU_P10V_3 (VREPLACE_UN_V4SI, "vreplace_un_v4si", CONST, vreplace_un_v4si)
> -BU_P10V_3 (VREPLACE_UN_UV4SI, "vreplace_un_uv4si", CONST, vreplace_un_v4si)
> -BU_P10V_3 (VREPLACE_UN_V4SF, "vreplace_un_v4sf", CONST, vreplace_un_v4sf)
> -BU_P10V_3 (VREPLACE_UN_V2DI, "vreplace_un_v2di", CONST, vreplace_un_v2di)
> -BU_P10V_3 (VREPLACE_UN_UV2DI, "vreplace_un_uv2di", CONST, vreplace_un_v2di)
> -BU_P10V_3 (VREPLACE_UN_V2DF, "vreplace_un_v2df", CONST, vreplace_un_v2df)
> -
> -BU_P10V_3 (VSLDB_V16QI, "vsldb_v16qi", CONST, vsldb_v16qi)
> -BU_P10V_3 (VSLDB_V8HI, "vsldb_v8hi", CONST, vsldb_v8hi)
> -BU_P10V_3 (VSLDB_V4SI, "vsldb_v4si", CONST, vsldb_v4si)
> -BU_P10V_3 (VSLDB_V2DI, "vsldb_v2di", CONST, vsldb_v2di)
> -
> -BU_P10V_3 (VSRDB_V16QI, "vsrdb_v16qi", CONST, vsrdb_v16qi)
> -BU_P10V_3 (VSRDB_V8HI, "vsrdb_v8hi", CONST, vsrdb_v8hi)
> -BU_P10V_3 (VSRDB_V4SI, "vsrdb_v4si", CONST, vsrdb_v4si)
> -BU_P10V_3 (VSRDB_V2DI, "vsrdb_v2di", CONST, vsrdb_v2di)
> -
> -BU_P10V_1 (VXXSPLTIW_V4SI, "vxxspltiw_v4si", CONST, xxspltiw_v4si)
> -BU_P10V_1 (VXXSPLTIW_V4SF, "vxxspltiw_v4sf", CONST, xxspltiw_v4sf)
> -
> -BU_P10V_1 (VXXSPLTID, "vxxspltidp", CONST, xxspltidp_v2df)
> -
> -BU_P10V_3 (VXXSPLTI32DX_V4SI, "vxxsplti32dx_v4si", CONST, xxsplti32dx_v4si)
> -BU_P10V_3 (VXXSPLTI32DX_V4SF, "vxxsplti32dx_v4sf", CONST, xxsplti32dx_v4sf)
> -
> -BU_P10V_3 (VXXBLEND_V16QI, "xxblend_v16qi", CONST, xxblend_v16qi)
> -BU_P10V_3 (VXXBLEND_V8HI, "xxblend_v8hi", CONST, xxblend_v8hi)
> -BU_P10V_3 (VXXBLEND_V4SI, "xxblend_v4si", CONST, xxblend_v4si)
> -BU_P10V_3 (VXXBLEND_V2DI, "xxblend_v2di", CONST, xxblend_v2di)
> -BU_P10V_3 (VXXBLEND_V4SF, "xxblend_v4sf", CONST, xxblend_v4sf)
> -BU_P10V_3 (VXXBLEND_V2DF, "xxblend_v2df", CONST, xxblend_v2df)
> -
> -BU_P10V_4 (VXXPERMX, "xxpermx", CONST, xxpermx)
> -
> -BU_P10V_1 (VSTRIBR, "vstribr", CONST, vstrir_v16qi)
> -BU_P10V_1 (VSTRIHR, "vstrihr", CONST, vstrir_v8hi)
> -BU_P10V_1 (VSTRIBL, "vstribl", CONST, vstril_v16qi)
> -BU_P10V_1 (VSTRIHL, "vstrihl", CONST, vstril_v8hi)
> -
> -BU_P10V_1 (VSTRIBR_P, "vstribr_p", CONST, vstrir_p_v16qi)
> -BU_P10V_1 (VSTRIHR_P, "vstrihr_p", CONST, vstrir_p_v8hi)
> -BU_P10V_1 (VSTRIBL_P, "vstribl_p", CONST, vstril_p_v16qi)
> -BU_P10V_1 (VSTRIHL_P, "vstrihl_p", CONST, vstril_p_v8hi)
> -
> -BU_P10_VSX_1 (XVTLSBB_ZEROS, "xvtlsbb_all_zeros", CONST, xvtlsbbz)
> -BU_P10_VSX_1 (XVTLSBB_ONES, "xvtlsbb_all_ones", CONST, xvtlsbbo)
> -
> -BU_P10V_1 (MTVSRBM, "mtvsrbm", CONST, vec_mtvsr_v16qi)
> -BU_P10V_1 (MTVSRHM, "mtvsrhm", CONST, vec_mtvsr_v8hi)
> -BU_P10V_1 (MTVSRWM, "mtvsrwm", CONST, vec_mtvsr_v4si)
> -BU_P10V_1 (MTVSRDM, "mtvsrdm", CONST, vec_mtvsr_v2di)
> -BU_P10V_1 (MTVSRQM, "mtvsrqm", CONST, vec_mtvsr_v1ti)
> -BU_P10V_2 (VCNTMBB, "cntmbb", CONST, vec_cntmb_v16qi)
> -BU_P10V_2 (VCNTMBH, "cntmbh", CONST, vec_cntmb_v8hi)
> -BU_P10V_2 (VCNTMBW, "cntmbw", CONST, vec_cntmb_v4si)
> -BU_P10V_2 (VCNTMBD, "cntmbd", CONST, vec_cntmb_v2di)
> -BU_P10V_1 (VEXPANDMB, "vexpandmb", CONST, vec_expand_v16qi)
> -BU_P10V_1 (VEXPANDMH, "vexpandmh", CONST, vec_expand_v8hi)
> -BU_P10V_1 (VEXPANDMW, "vexpandmw", CONST, vec_expand_v4si)
> -BU_P10V_1 (VEXPANDMD, "vexpandmd", CONST, vec_expand_v2di)
> -BU_P10V_1 (VEXPANDMQ, "vexpandmq", CONST, vec_expand_v1ti)
> -BU_P10V_1 (VEXTRACTMB, "vextractmb", CONST, vec_extract_v16qi)
> -BU_P10V_1 (VEXTRACTMH, "vextractmh", CONST, vec_extract_v8hi)
> -BU_P10V_1 (VEXTRACTMW, "vextractmw", CONST, vec_extract_v4si)
> -BU_P10V_1 (VEXTRACTMD, "vextractmd", CONST, vec_extract_v2di)
> -BU_P10V_1 (VEXTRACTMQ, "vextractmq", CONST, vec_extract_v1ti)
> +BU_P10V_AV_2 (VCLRLB, "vclrlb", CONST, vclrlb)
> +BU_P10V_AV_2 (VCLRRB, "vclrrb", CONST, vclrrb)
> +BU_P10V_AV_2 (VCFUGED, "vcfuged", CONST, vcfuged)
> +BU_P10V_AV_2 (VCLZDM, "vclzdm", CONST, vclzdm)
> +BU_P10V_AV_2 (VCTZDM, "vctzdm", CONST, vctzdm)
> +BU_P10V_AV_2 (VPDEPD, "vpdepd", CONST, vpdepd)
> +BU_P10V_AV_2 (VPEXTD, "vpextd", CONST, vpextd)
> +BU_P10V_AV_2 (VGNB, "vgnb", CONST, vgnb)
> +BU_P10V_VSX_4 (XXEVAL, "xxeval", CONST, xxeval)
> +BU_P10V_VSX_2 (XXGENPCVM_V16QI, "xxgenpcvm_v16qi", CONST, xxgenpcvm_v16qi)
> +BU_P10V_VSX_2 (XXGENPCVM_V8HI, "xxgenpcvm_v8hi", CONST, xxgenpcvm_v8hi)
> +BU_P10V_VSX_2 (XXGENPCVM_V4SI, "xxgenpcvm_v4si", CONST, xxgenpcvm_v4si)
> +BU_P10V_VSX_2 (XXGENPCVM_V2DI, "xxgenpcvm_v2di", CONST, xxgenpcvm_v2di)
> +
> +BU_P10V_AV_3 (VEXTRACTBL, "vextdubvlx", CONST, vextractlv16qi)
> +BU_P10V_AV_3 (VEXTRACTHL, "vextduhvlx", CONST, vextractlv8hi)
> +BU_P10V_AV_3 (VEXTRACTWL, "vextduwvlx", CONST, vextractlv4si)
> +BU_P10V_AV_3 (VEXTRACTDL, "vextddvlx", CONST, vextractlv2di)
> +
> +BU_P10V_AV_3 (VEXTRACTBR, "vextdubvhx", CONST, vextractrv16qi)
> +BU_P10V_AV_3 (VEXTRACTHR, "vextduhvhx", CONST, vextractrv8hi)
> +BU_P10V_AV_3 (VEXTRACTWR, "vextduwvhx", CONST, vextractrv4si)
> +BU_P10V_AV_3 (VEXTRACTDR, "vextddvhx", CONST, vextractrv2di)
> +
> +BU_P10V_AV_3 (VINSERTGPRBL, "vinsgubvlx", CONST, vinsertgl_v16qi)
> +BU_P10V_AV_3 (VINSERTGPRHL, "vinsguhvlx", CONST, vinsertgl_v8hi)
> +BU_P10V_AV_3 (VINSERTGPRWL, "vinsguwvlx", CONST, vinsertgl_v4si)
> +BU_P10V_AV_3 (VINSERTGPRDL, "vinsgudvlx", CONST, vinsertgl_v2di)
> +BU_P10V_AV_3 (VINSERTVPRBL, "vinsvubvlx", CONST, vinsertvl_v16qi)
> +BU_P10V_AV_3 (VINSERTVPRHL, "vinsvuhvlx", CONST, vinsertvl_v8hi)
> +BU_P10V_AV_3 (VINSERTVPRWL, "vinsvuwvlx", CONST, vinsertvl_v4si)
> +
> +BU_P10V_AV_3 (VINSERTGPRBR, "vinsgubvrx", CONST, vinsertgr_v16qi)
> +BU_P10V_AV_3 (VINSERTGPRHR, "vinsguhvrx", CONST, vinsertgr_v8hi)
> +BU_P10V_AV_3 (VINSERTGPRWR, "vinsguwvrx", CONST, vinsertgr_v4si)
> +BU_P10V_AV_3 (VINSERTGPRDR, "vinsgudvrx", CONST, vinsertgr_v2di)
> +BU_P10V_AV_3 (VINSERTVPRBR, "vinsvubvrx", CONST, vinsertvr_v16qi)
> +BU_P10V_AV_3 (VINSERTVPRHR, "vinsvuhvrx", CONST, vinsertvr_v8hi)
> +BU_P10V_AV_3 (VINSERTVPRWR, "vinsvuwvrx", CONST, vinsertvr_v4si)
> +
> +BU_P10V_AV_3 (VREPLACE_ELT_V4SI, "vreplace_v4si", CONST, vreplace_elt_v4si)
> +BU_P10V_AV_3 (VREPLACE_ELT_UV4SI, "vreplace_uv4si", CONST, vreplace_elt_v4si)
> +BU_P10V_AV_3 (VREPLACE_ELT_V4SF, "vreplace_v4sf", CONST, vreplace_elt_v4sf)
> +BU_P10V_AV_3 (VREPLACE_ELT_V2DI, "vreplace_v2di", CONST, vreplace_elt_v2di)
> +BU_P10V_AV_3 (VREPLACE_ELT_UV2DI, "vreplace_uv2di", CONST, vreplace_elt_v2di)
> +BU_P10V_AV_3 (VREPLACE_ELT_V2DF, "vreplace_v2df", CONST, vreplace_elt_v2df)
> +
> +BU_P10V_AV_3 (VREPLACE_UN_V4SI, "vreplace_un_v4si", CONST, vreplace_un_v4si)
> +BU_P10V_AV_3 (VREPLACE_UN_UV4SI, "vreplace_un_uv4si", CONST, vreplace_un_v4si)
> +BU_P10V_AV_3 (VREPLACE_UN_V4SF, "vreplace_un_v4sf", CONST, vreplace_un_v4sf)
> +BU_P10V_AV_3 (VREPLACE_UN_V2DI, "vreplace_un_v2di", CONST, vreplace_un_v2di)
> +BU_P10V_AV_3 (VREPLACE_UN_UV2DI, "vreplace_un_uv2di", CONST, vreplace_un_v2di)
> +BU_P10V_AV_3 (VREPLACE_UN_V2DF, "vreplace_un_v2df", CONST, vreplace_un_v2df)
> +
> +BU_P10V_AV_3 (VSLDB_V16QI, "vsldb_v16qi", CONST, vsldb_v16qi)
> +BU_P10V_AV_3 (VSLDB_V8HI, "vsldb_v8hi", CONST, vsldb_v8hi)
> +BU_P10V_AV_3 (VSLDB_V4SI, "vsldb_v4si", CONST, vsldb_v4si)
> +BU_P10V_AV_3 (VSLDB_V2DI, "vsldb_v2di", CONST, vsldb_v2di)
> +
> +BU_P10V_AV_3 (VSRDB_V16QI, "vsrdb_v16qi", CONST, vsrdb_v16qi)
> +BU_P10V_AV_3 (VSRDB_V8HI, "vsrdb_v8hi", CONST, vsrdb_v8hi)
> +BU_P10V_AV_3 (VSRDB_V4SI, "vsrdb_v4si", CONST, vsrdb_v4si)
> +BU_P10V_AV_3 (VSRDB_V2DI, "vsrdb_v2di", CONST, vsrdb_v2di)
> +
> +BU_P10V_VSX_1 (VXXSPLTIW_V4SI, "vxxspltiw_v4si", CONST, xxspltiw_v4si)
> +BU_P10V_VSX_1 (VXXSPLTIW_V4SF, "vxxspltiw_v4sf", CONST, xxspltiw_v4sf)
> +
> +BU_P10V_VSX_1 (VXXSPLTID, "vxxspltidp", CONST, xxspltidp_v2df)
> +
> +BU_P10V_VSX_3 (VXXSPLTI32DX_V4SI, "vxxsplti32dx_v4si", CONST, xxsplti32dx_v4si)
> +BU_P10V_VSX_3 (VXXSPLTI32DX_V4SF, "vxxsplti32dx_v4sf", CONST, xxsplti32dx_v4sf)
> +
> +BU_P10V_VSX_3 (VXXBLEND_V16QI, "xxblend_v16qi", CONST, xxblend_v16qi)
> +BU_P10V_VSX_3 (VXXBLEND_V8HI, "xxblend_v8hi", CONST, xxblend_v8hi)
> +BU_P10V_VSX_3 (VXXBLEND_V4SI, "xxblend_v4si", CONST, xxblend_v4si)
> +BU_P10V_VSX_3 (VXXBLEND_V2DI, "xxblend_v2di", CONST, xxblend_v2di)
> +BU_P10V_VSX_3 (VXXBLEND_V4SF, "xxblend_v4sf", CONST, xxblend_v4sf)
> +BU_P10V_VSX_3 (VXXBLEND_V2DF, "xxblend_v2df", CONST, xxblend_v2df)
> +
> +BU_P10V_VSX_4 (VXXPERMX, "xxpermx", CONST, xxpermx)
> +
> +BU_P10V_AV_1 (VSTRIBR, "vstribr", CONST, vstrir_v16qi)
> +BU_P10V_AV_1 (VSTRIHR, "vstrihr", CONST, vstrir_v8hi)
> +BU_P10V_AV_1 (VSTRIBL, "vstribl", CONST, vstril_v16qi)
> +BU_P10V_AV_1 (VSTRIHL, "vstrihl", CONST, vstril_v8hi)
> +
> +BU_P10V_AV_1 (VSTRIBR_P, "vstribr_p", CONST, vstrir_p_v16qi)
> +BU_P10V_AV_1 (VSTRIHR_P, "vstrihr_p", CONST, vstrir_p_v8hi)
> +BU_P10V_AV_1 (VSTRIBL_P, "vstribl_p", CONST, vstril_p_v16qi)
> +BU_P10V_AV_1 (VSTRIHL_P, "vstrihl_p", CONST, vstril_p_v8hi)
> +
> +BU_P10V_VSX_1 (XVTLSBB_ZEROS, "xvtlsbb_all_zeros", CONST, xvtlsbbz)
> +BU_P10V_VSX_1 (XVTLSBB_ONES, "xvtlsbb_all_ones", CONST, xvtlsbbo)
> +
> +BU_P10V_AV_1 (MTVSRBM, "mtvsrbm", CONST, vec_mtvsr_v16qi)
> +BU_P10V_AV_1 (MTVSRHM, "mtvsrhm", CONST, vec_mtvsr_v8hi)
> +BU_P10V_AV_1 (MTVSRWM, "mtvsrwm", CONST, vec_mtvsr_v4si)
> +BU_P10V_AV_1 (MTVSRDM, "mtvsrdm", CONST, vec_mtvsr_v2di)
> +BU_P10V_AV_1 (MTVSRQM, "mtvsrqm", CONST, vec_mtvsr_v1ti)
> +BU_P10V_AV_2 (VCNTMBB, "cntmbb", CONST, vec_cntmb_v16qi)
> +BU_P10V_AV_2 (VCNTMBH, "cntmbh", CONST, vec_cntmb_v8hi)
> +BU_P10V_AV_2 (VCNTMBW, "cntmbw", CONST, vec_cntmb_v4si)
> +BU_P10V_AV_2 (VCNTMBD, "cntmbd", CONST, vec_cntmb_v2di)
> +BU_P10V_AV_1 (VEXPANDMB, "vexpandmb", CONST, vec_expand_v16qi)
> +BU_P10V_AV_1 (VEXPANDMH, "vexpandmh", CONST, vec_expand_v8hi)
> +BU_P10V_AV_1 (VEXPANDMW, "vexpandmw", CONST, vec_expand_v4si)
> +BU_P10V_AV_1 (VEXPANDMD, "vexpandmd", CONST, vec_expand_v2di)
> +BU_P10V_AV_1 (VEXPANDMQ, "vexpandmq", CONST, vec_expand_v1ti)
> +BU_P10V_AV_1 (VEXTRACTMB, "vextractmb", CONST, vec_extract_v16qi)
> +BU_P10V_AV_1 (VEXTRACTMH, "vextractmh", CONST, vec_extract_v8hi)
> +BU_P10V_AV_1 (VEXTRACTMW, "vextractmw", CONST, vec_extract_v4si)
> +BU_P10V_AV_1 (VEXTRACTMD, "vextractmd", CONST, vec_extract_v2di)
> +BU_P10V_AV_1 (VEXTRACTMQ, "vextractmq", CONST, vec_extract_v1ti)
>
> /* Overloaded vector builtins for ISA 3.1 (power10). */
> BU_P10_OVERLOAD_2 (CLRL, "clrl")
> @@ -2998,8 +3023,8 @@ BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS,
> RS6000_BTC_MISC)
>
> /* POWER10 MMA builtins. */
> -BU_VSX_1 (XVCVBF16SP, "xvcvbf16sp", MISC, vsx_xvcvbf16sp)
> -BU_VSX_1 (XVCVSPBF16, "xvcvspbf16", MISC, vsx_xvcvspbf16)
> +BU_P10V_VSX_1 (XVCVBF16SP, "xvcvbf16sp", CONST, vsx_xvcvbf16sp)
> +BU_P10V_VSX_1 (XVCVSPBF16, "xvcvspbf16", CONST, vsx_xvcvspbf16)
>
> BU_MMA_1 (XXMFACC, "xxmfacc", QUAD, mma_xxmfacc)
> BU_MMA_1 (XXMTACC, "xxmtacc", QUAD, mma_xxmtacc)
> diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
> index 2fad3d94706..f5982907e90 100644
> --- a/gcc/config/rs6000/rs6000-c.c
> +++ b/gcc/config/rs6000/rs6000-c.c
> @@ -1801,12 +1801,12 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
> }
> }
> else if ((fcode == P10_BUILTIN_VEC_XXEVAL)
> - || (fcode == P10_BUILTIN_VXXPERMX))
> + || (fcode == P10V_BUILTIN_VXXPERMX))
> {
> signed char op3_type;
>
> /* Need to special case P10_BUILTIN_VEC_XXEVAL and
> - P10_BUILTIN_VXXPERMX because they take 4 arguments and the
> + P10V_BUILTIN_VXXPERMX because they take 4 arguments and the
> existing infrastructure only handles three. */
> if (nargs != 4)
> {
> @@ -1821,7 +1821,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
> {
> if (fcode == P10_BUILTIN_VEC_XXEVAL)
> op3_type = desc->op3;
> - else /* P10_BUILTIN_VXXPERMX */
> + else /* P10V_BUILTIN_VXXPERMX */
> op3_type = RS6000_BTI_V16QI;
>
> if (rs6000_builtin_type_compatible (types[0], desc->op1)
> diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
> index 189497efb45..9cd43d7e468 100644
> --- a/gcc/config/rs6000/rs6000-call.c
> +++ b/gcc/config/rs6000/rs6000-call.c
> @@ -5528,366 +5528,366 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
> RS6000_BTI_INTSI, RS6000_BTI_INTSI },
>
> /* Overloaded built-in functions for ISA3.1 (power10). */
> - { P10_BUILTIN_VEC_CLRL, P10_BUILTIN_VCLRLB,
> + { P10_BUILTIN_VEC_CLRL, P10V_BUILTIN_VCLRLB,
> RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 },
> - { P10_BUILTIN_VEC_CLRL, P10_BUILTIN_VCLRLB,
> + { P10_BUILTIN_VEC_CLRL, P10V_BUILTIN_VCLRLB,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
> RS6000_BTI_UINTSI, 0 },
> - { P10_BUILTIN_VEC_CLRR, P10_BUILTIN_VCLRRB,
> + { P10_BUILTIN_VEC_CLRR, P10V_BUILTIN_VCLRRB,
> RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 },
> - { P10_BUILTIN_VEC_CLRR, P10_BUILTIN_VCLRRB,
> + { P10_BUILTIN_VEC_CLRR, P10V_BUILTIN_VCLRRB,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
> RS6000_BTI_UINTSI, 0 },
>
> - { P10_BUILTIN_VEC_GNB, P10_BUILTIN_VGNB, RS6000_BTI_unsigned_long_long,
> + { P10_BUILTIN_VEC_GNB, P10V_BUILTIN_VGNB, RS6000_BTI_unsigned_long_long,
> RS6000_BTI_unsigned_V1TI, RS6000_BTI_UINTQI, 0 },
> - { P10_BUILTIN_VEC_XXGENPCVM, P10_BUILTIN_XXGENPCVM_V2DI,
> + { P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V2DI,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 },
> - { P10_BUILTIN_VEC_XXGENPCVM, P10_BUILTIN_XXGENPCVM_V4SI,
> + { P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V4SI,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 },
> - { P10_BUILTIN_VEC_XXGENPCVM, P10_BUILTIN_XXGENPCVM_V8HI,
> + { P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V8HI,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 },
> - { P10_BUILTIN_VEC_XXGENPCVM, P10_BUILTIN_XXGENPCVM_V16QI,
> + { P10_BUILTIN_VEC_XXGENPCVM, P10V_BUILTIN_XXGENPCVM_V16QI,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
> RS6000_BTI_INTSI, 0 },
>
> /* The overloaded XXEVAL definitions are handled specially because the
> fourth unsigned char operand is not encoded in this table. */
> - { P10_BUILTIN_VEC_XXEVAL, P10_BUILTIN_XXEVAL,
> + { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
> - { P10_BUILTIN_VEC_XXEVAL, P10_BUILTIN_XXEVAL,
> + { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
> - { P10_BUILTIN_VEC_XXEVAL, P10_BUILTIN_XXEVAL,
> + { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
> - { P10_BUILTIN_VEC_XXEVAL, P10_BUILTIN_XXEVAL,
> + { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
> - { P10_BUILTIN_VEC_XXEVAL, P10_BUILTIN_XXEVAL,
> + { P10_BUILTIN_VEC_XXEVAL, P10V_BUILTIN_XXEVAL,
> RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI,
> RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI },
>
> /* The overloaded XXPERMX definitions are handled specially because the
> fourth unsigned char operand is not encoded in this table. */
> - { P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
> + { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
> RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI,
> RS6000_BTI_unsigned_V16QI },
> - { P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
> + { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
> - { P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
> + { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
> RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI,
> RS6000_BTI_unsigned_V16QI },
> - { P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
> + { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI },
> - { P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
> + { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
> RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI,
> RS6000_BTI_unsigned_V16QI },
> - { P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
> + { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI },
> - { P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
> + { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
> RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI,
> RS6000_BTI_unsigned_V16QI },
> - { P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
> + { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI },
> - { P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
> + { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
> RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF,
> RS6000_BTI_unsigned_V16QI },
> - { P10_BUILTIN_VEC_XXPERMX, P10_BUILTIN_VXXPERMX,
> + { P10_BUILTIN_VEC_XXPERMX, P10V_BUILTIN_VXXPERMX,
> RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF,
> RS6000_BTI_unsigned_V16QI },
>
> - { P10_BUILTIN_VEC_EXTRACTL, P10_BUILTIN_VEXTRACTBL,
> + { P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTBL,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_EXTRACTL, P10_BUILTIN_VEXTRACTHL,
> + { P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTHL,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V8HI,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_EXTRACTL, P10_BUILTIN_VEXTRACTWL,
> + { P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTWL,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_EXTRACTL, P10_BUILTIN_VEXTRACTDL,
> + { P10_BUILTIN_VEC_EXTRACTL, P10V_BUILTIN_VEXTRACTDL,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI },
>
> - { P10_BUILTIN_VEC_INSERTL, P10_BUILTIN_VINSERTGPRBL,
> + { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRBL,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI },
> - { P10_BUILTIN_VEC_INSERTL, P10_BUILTIN_VINSERTGPRHL,
> + { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRHL,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTHI,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTSI },
> - { P10_BUILTIN_VEC_INSERTL, P10_BUILTIN_VINSERTGPRWL,
> + { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRWL,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI },
> - { P10_BUILTIN_VEC_INSERTL, P10_BUILTIN_VINSERTGPRDL,
> + { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTGPRDL,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTDI,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTSI },
> - { P10_BUILTIN_VEC_INSERTL, P10_BUILTIN_VINSERTVPRBL,
> + { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTVPRBL,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_INSERTL, P10_BUILTIN_VINSERTVPRHL,
> + { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTVPRHL,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_INSERTL, P10_BUILTIN_VINSERTVPRWL,
> + { P10_BUILTIN_VEC_INSERTL, P10V_BUILTIN_VINSERTVPRWL,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
>
> - { P10_BUILTIN_VEC_EXTRACTH, P10_BUILTIN_VEXTRACTBR,
> + { P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTBR,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_EXTRACTH, P10_BUILTIN_VEXTRACTHR,
> + { P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTHR,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V8HI,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_EXTRACTH, P10_BUILTIN_VEXTRACTWR,
> + { P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTWR,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_EXTRACTH, P10_BUILTIN_VEXTRACTDR,
> + { P10_BUILTIN_VEC_EXTRACTH, P10V_BUILTIN_VEXTRACTDR,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI },
>
> - { P10_BUILTIN_VEC_INSERTH, P10_BUILTIN_VINSERTGPRBR,
> + { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRBR,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTSI },
> - { P10_BUILTIN_VEC_INSERTH, P10_BUILTIN_VINSERTGPRHR,
> + { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRHR,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTHI,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTSI },
> - { P10_BUILTIN_VEC_INSERTH, P10_BUILTIN_VINSERTGPRWR,
> + { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRWR,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTSI },
> - { P10_BUILTIN_VEC_INSERTH, P10_BUILTIN_VINSERTGPRDR,
> + { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTGPRDR,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTDI,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTSI },
> - { P10_BUILTIN_VEC_INSERTH, P10_BUILTIN_VINSERTVPRBR,
> + { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTVPRBR,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_INSERTH, P10_BUILTIN_VINSERTVPRHR,
> + { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTVPRHR,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_INSERTH, P10_BUILTIN_VINSERTVPRWR,
> + { P10_BUILTIN_VEC_INSERTH, P10V_BUILTIN_VINSERTVPRWR,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
>
> - { P10_BUILTIN_VEC_REPLACE_ELT, P10_BUILTIN_VREPLACE_ELT_UV4SI,
> + { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_UV4SI,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
> RS6000_BTI_UINTSI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_REPLACE_ELT, P10_BUILTIN_VREPLACE_ELT_V4SI,
> + { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V4SI,
> RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTQI },
> - { P10_BUILTIN_VEC_REPLACE_ELT, P10_BUILTIN_VREPLACE_ELT_V4SF,
> + { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V4SF,
> RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_float, RS6000_BTI_INTQI },
> - { P10_BUILTIN_VEC_REPLACE_ELT, P10_BUILTIN_VREPLACE_ELT_UV2DI,
> + { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_UV2DI,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
> RS6000_BTI_UINTDI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_REPLACE_ELT, P10_BUILTIN_VREPLACE_ELT_V2DI,
> + { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V2DI,
> RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTDI, RS6000_BTI_INTQI },
> - { P10_BUILTIN_VEC_REPLACE_ELT, P10_BUILTIN_VREPLACE_ELT_V2DF,
> + { P10_BUILTIN_VEC_REPLACE_ELT, P10V_BUILTIN_VREPLACE_ELT_V2DF,
> RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_double, RS6000_BTI_INTQI },
>
> - { P10_BUILTIN_VEC_REPLACE_UN, P10_BUILTIN_VREPLACE_UN_UV4SI,
> + { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_UV4SI,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
> RS6000_BTI_UINTSI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_REPLACE_UN, P10_BUILTIN_VREPLACE_UN_V4SI,
> + { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V4SI,
> RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTQI },
> - { P10_BUILTIN_VEC_REPLACE_UN, P10_BUILTIN_VREPLACE_UN_V4SF,
> + { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V4SF,
> RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_float, RS6000_BTI_INTQI },
> - { P10_BUILTIN_VEC_REPLACE_UN, P10_BUILTIN_VREPLACE_UN_UV2DI,
> + { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_UV2DI,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
> RS6000_BTI_UINTDI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_REPLACE_UN, P10_BUILTIN_VREPLACE_UN_V2DI,
> + { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V2DI,
> RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTDI, RS6000_BTI_INTQI },
> - { P10_BUILTIN_VEC_REPLACE_UN, P10_BUILTIN_VREPLACE_UN_V2DF,
> + { P10_BUILTIN_VEC_REPLACE_UN, P10V_BUILTIN_VREPLACE_UN_V2DF,
> RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_double, RS6000_BTI_INTQI },
>
> - { P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V16QI,
> + { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V16QI,
> RS6000_BTI_V16QI, RS6000_BTI_V16QI,
> RS6000_BTI_V16QI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V16QI,
> + { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V16QI,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V8HI,
> + { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V8HI,
> RS6000_BTI_V8HI, RS6000_BTI_V8HI,
> RS6000_BTI_V8HI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V8HI,
> + { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V8HI,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V4SI,
> + { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V4SI,
> RS6000_BTI_V4SI, RS6000_BTI_V4SI,
> RS6000_BTI_V4SI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V4SI,
> + { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V4SI,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V2DI,
> + { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V2DI,
> RS6000_BTI_V2DI, RS6000_BTI_V2DI,
> RS6000_BTI_V2DI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_SLDB, P10_BUILTIN_VSLDB_V2DI,
> + { P10_BUILTIN_VEC_SLDB, P10V_BUILTIN_VSLDB_V2DI,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI },
>
> - { P10_BUILTIN_VEC_XXSPLTIW, P10_BUILTIN_VXXSPLTIW_V4SI,
> + { P10_BUILTIN_VEC_XXSPLTIW, P10V_BUILTIN_VXXSPLTIW_V4SI,
> RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0, 0 },
> - { P10_BUILTIN_VEC_XXSPLTIW, P10_BUILTIN_VXXSPLTIW_V4SF,
> + { P10_BUILTIN_VEC_XXSPLTIW, P10V_BUILTIN_VXXSPLTIW_V4SF,
> RS6000_BTI_V4SF, RS6000_BTI_float, 0, 0 },
>
> - { P10_BUILTIN_VEC_XXSPLTID, P10_BUILTIN_VXXSPLTID,
> + { P10_BUILTIN_VEC_XXSPLTID, P10V_BUILTIN_VXXSPLTID,
> RS6000_BTI_V2DF, RS6000_BTI_float, 0, 0 },
>
> - { P10_BUILTIN_VEC_XXSPLTI32DX, P10_BUILTIN_VXXSPLTI32DX_V4SI,
> + { P10_BUILTIN_VEC_XXSPLTI32DX, P10V_BUILTIN_VXXSPLTI32DX_V4SI,
> RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_UINTQI, RS6000_BTI_INTSI },
> - { P10_BUILTIN_VEC_XXSPLTI32DX, P10_BUILTIN_VXXSPLTI32DX_V4SI,
> + { P10_BUILTIN_VEC_XXSPLTI32DX, P10V_BUILTIN_VXXSPLTI32DX_V4SI,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI,
> RS6000_BTI_UINTSI },
> - { P10_BUILTIN_VEC_XXSPLTI32DX, P10_BUILTIN_VXXSPLTI32DX_V4SF,
> + { P10_BUILTIN_VEC_XXSPLTI32DX, P10V_BUILTIN_VXXSPLTI32DX_V4SF,
> RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_UINTQI, RS6000_BTI_float },
>
> - { P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V16QI,
> + { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V16QI,
> RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI,
> RS6000_BTI_unsigned_V16QI },
> - { P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V16QI,
> + { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V16QI,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI },
> - { P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V8HI,
> + { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V8HI,
> RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI,
> RS6000_BTI_unsigned_V8HI },
> - { P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V8HI,
> + { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V8HI,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI },
> - { P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V4SI,
> + { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V4SI,
> RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI,
> RS6000_BTI_unsigned_V4SI },
> - { P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V4SI,
> + { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V4SI,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI },
> - { P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V2DI,
> + { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V2DI,
> RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI,
> RS6000_BTI_unsigned_V2DI },
> - { P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V2DI,
> + { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V2DI,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI },
> - { P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V4SF,
> + { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V4SF,
> RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF,
> RS6000_BTI_unsigned_V4SI },
> - { P10_BUILTIN_VEC_XXBLEND, P10_BUILTIN_VXXBLEND_V2DF,
> + { P10_BUILTIN_VEC_XXBLEND, P10V_BUILTIN_VXXBLEND_V2DF,
> RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF,
> RS6000_BTI_unsigned_V2DI },
>
> - { P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V16QI,
> + { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V16QI,
> RS6000_BTI_V16QI, RS6000_BTI_V16QI,
> RS6000_BTI_V16QI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V16QI,
> + { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V16QI,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V8HI,
> + { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V8HI,
> RS6000_BTI_V8HI, RS6000_BTI_V8HI,
> RS6000_BTI_V8HI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V8HI,
> + { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V8HI,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V4SI,
> + { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V4SI,
> RS6000_BTI_V4SI, RS6000_BTI_V4SI,
> RS6000_BTI_V4SI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V4SI,
> + { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V4SI,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V2DI,
> + { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V2DI,
> RS6000_BTI_V2DI, RS6000_BTI_V2DI,
> RS6000_BTI_V2DI, RS6000_BTI_UINTQI },
> - { P10_BUILTIN_VEC_SRDB, P10_BUILTIN_VSRDB_V2DI,
> + { P10_BUILTIN_VEC_SRDB, P10V_BUILTIN_VSRDB_V2DI,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI },
>
> - { P10_BUILTIN_VEC_VSTRIL, P10_BUILTIN_VSTRIBL,
> + { P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIBL,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
> - { P10_BUILTIN_VEC_VSTRIL, P10_BUILTIN_VSTRIBL,
> + { P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIBL,
> RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
>
> - { P10_BUILTIN_VEC_VSTRIL, P10_BUILTIN_VSTRIHL,
> + { P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIHL,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
> - { P10_BUILTIN_VEC_VSTRIL, P10_BUILTIN_VSTRIHL,
> + { P10_BUILTIN_VEC_VSTRIL, P10V_BUILTIN_VSTRIHL,
> RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
>
> - { P10_BUILTIN_VEC_VSTRIL_P, P10_BUILTIN_VSTRIBL_P,
> + { P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIBL_P,
> RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
> - { P10_BUILTIN_VEC_VSTRIL_P, P10_BUILTIN_VSTRIBL_P,
> + { P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIBL_P,
> RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
>
> - { P10_BUILTIN_VEC_VSTRIL_P, P10_BUILTIN_VSTRIHL_P,
> + { P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIHL_P,
> RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 },
> - { P10_BUILTIN_VEC_VSTRIL_P, P10_BUILTIN_VSTRIHL_P,
> + { P10_BUILTIN_VEC_VSTRIL_P, P10V_BUILTIN_VSTRIHL_P,
> RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
>
> - { P10_BUILTIN_VEC_VSTRIR, P10_BUILTIN_VSTRIBR,
> + { P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIBR,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
> - { P10_BUILTIN_VEC_VSTRIR, P10_BUILTIN_VSTRIBR,
> + { P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIBR,
> RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
>
> - { P10_BUILTIN_VEC_VSTRIR, P10_BUILTIN_VSTRIHR,
> + { P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIHR,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
> - { P10_BUILTIN_VEC_VSTRIR, P10_BUILTIN_VSTRIHR,
> + { P10_BUILTIN_VEC_VSTRIR, P10V_BUILTIN_VSTRIHR,
> RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 },
>
> - { P10_BUILTIN_VEC_VSTRIR_P, P10_BUILTIN_VSTRIBR_P,
> + { P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIBR_P,
> RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
> - { P10_BUILTIN_VEC_VSTRIR_P, P10_BUILTIN_VSTRIBR_P,
> + { P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIBR_P,
> RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 },
>
> - { P10_BUILTIN_VEC_VSTRIR_P, P10_BUILTIN_VSTRIHR_P,
> + { P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIHR_P,
> RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 },
> - { P10_BUILTIN_VEC_VSTRIR_P, P10_BUILTIN_VSTRIHR_P,
> + { P10_BUILTIN_VEC_VSTRIR_P, P10V_BUILTIN_VSTRIHR_P,
> RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 },
>
> - { P10_BUILTIN_VEC_MTVSRBM, P10_BUILTIN_MTVSRBM,
> + { P10_BUILTIN_VEC_MTVSRBM, P10V_BUILTIN_MTVSRBM,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI, 0, 0 },
> - { P10_BUILTIN_VEC_MTVSRHM, P10_BUILTIN_MTVSRHM,
> + { P10_BUILTIN_VEC_MTVSRHM, P10V_BUILTIN_MTVSRHM,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTDI, 0, 0 },
> - { P10_BUILTIN_VEC_MTVSRWM, P10_BUILTIN_MTVSRWM,
> + { P10_BUILTIN_VEC_MTVSRWM, P10V_BUILTIN_MTVSRWM,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTDI, 0, 0 },
> - { P10_BUILTIN_VEC_MTVSRDM, P10_BUILTIN_MTVSRDM,
> + { P10_BUILTIN_VEC_MTVSRDM, P10V_BUILTIN_MTVSRDM,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTDI, 0, 0 },
> - { P10_BUILTIN_VEC_MTVSRQM, P10_BUILTIN_MTVSRQM,
> + { P10_BUILTIN_VEC_MTVSRQM, P10V_BUILTIN_MTVSRQM,
> RS6000_BTI_unsigned_V1TI, RS6000_BTI_UINTDI, 0, 0 },
>
> - { P10_BUILTIN_VEC_VCNTM, P10_BUILTIN_VCNTMBB,
> + { P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBB,
> RS6000_BTI_unsigned_long_long,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI, 0 },
> - { P10_BUILTIN_VEC_VCNTM, P10_BUILTIN_VCNTMBH,
> + { P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBH,
> RS6000_BTI_unsigned_long_long,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI, 0 },
> - { P10_BUILTIN_VEC_VCNTM, P10_BUILTIN_VCNTMBW,
> + { P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBW,
> RS6000_BTI_unsigned_long_long,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI, 0 },
> - { P10_BUILTIN_VEC_VCNTM, P10_BUILTIN_VCNTMBD,
> + { P10_BUILTIN_VEC_VCNTM, P10V_BUILTIN_VCNTMBD,
> RS6000_BTI_unsigned_long_long,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI, 0 },
>
> - { P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMB,
> + { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMB,
> RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 },
> - { P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMH,
> + { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMH,
> RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 },
> - { P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMW,
> + { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMW,
> RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 },
> - { P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMD,
> + { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMD,
> RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
> - { P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMQ,
> + { P10_BUILTIN_VEC_VEXPANDM, P10V_BUILTIN_VEXPANDMQ,
> RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 },
>
> - { P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMB,
> + { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMB,
> RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
> - { P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMH,
> + { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMH,
> RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 },
> - { P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMW,
> + { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMW,
> RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, 0, 0 },
> - { P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMD,
> + { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMD,
> RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, 0, 0 },
> - { P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMQ,
> + { P10_BUILTIN_VEC_VEXTRACTM, P10V_BUILTIN_VEXTRACTMQ,
> RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, 0, 0 },
>
> - { P10_BUILTIN_VEC_XVTLSBB_ZEROS, P10_BUILTIN_XVTLSBB_ZEROS,
> + { P10_BUILTIN_VEC_XVTLSBB_ZEROS, P10V_BUILTIN_XVTLSBB_ZEROS,
> RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
> - { P10_BUILTIN_VEC_XVTLSBB_ONES, P10_BUILTIN_XVTLSBB_ONES,
> + { P10_BUILTIN_VEC_XVTLSBB_ONES, P10V_BUILTIN_XVTLSBB_ONES,
> RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 },
>
> { RS6000_BUILTIN_NONE, RS6000_BUILTIN_NONE, 0, 0, 0, 0 }
> @@ -13937,7 +13937,7 @@ builtin_quaternary_function_type (machine_mode mode_ret,
>
> switch (builtin) {
>
> - case P10_BUILTIN_XXEVAL:
> + case P10V_BUILTIN_XXEVAL:
> gcc_assert ((mode_ret == V2DImode)
> && (mode_arg0 == V2DImode)
> && (mode_arg1 == V2DImode)
> @@ -13946,7 +13946,7 @@ builtin_quaternary_function_type (machine_mode mode_ret,
> function_type = xxeval_type;
> break;
>
> - case P10_BUILTIN_VXXPERMX:
> + case P10V_BUILTIN_VXXPERMX:
> gcc_assert ((mode_ret == V2DImode)
> && (mode_arg0 == V2DImode)
> && (mode_arg1 == V2DImode)
> @@ -14004,22 +14004,22 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
> case P8V_BUILTIN_VGBBD:
> case MISC_BUILTIN_CDTBCD:
> case MISC_BUILTIN_CBCDTD:
> - case VSX_BUILTIN_XVCVSPBF16:
> - case VSX_BUILTIN_XVCVBF16SP:
> - case P10_BUILTIN_MTVSRBM:
> - case P10_BUILTIN_MTVSRHM:
> - case P10_BUILTIN_MTVSRWM:
> - case P10_BUILTIN_MTVSRDM:
> - case P10_BUILTIN_MTVSRQM:
> - case P10_BUILTIN_VCNTMBB:
> - case P10_BUILTIN_VCNTMBH:
> - case P10_BUILTIN_VCNTMBW:
> - case P10_BUILTIN_VCNTMBD:
> - case P10_BUILTIN_VEXPANDMB:
> - case P10_BUILTIN_VEXPANDMH:
> - case P10_BUILTIN_VEXPANDMW:
> - case P10_BUILTIN_VEXPANDMD:
> - case P10_BUILTIN_VEXPANDMQ:
> + case P10V_BUILTIN_XVCVSPBF16:
> + case P10V_BUILTIN_XVCVBF16SP:
> + case P10V_BUILTIN_MTVSRBM:
> + case P10V_BUILTIN_MTVSRHM:
> + case P10V_BUILTIN_MTVSRWM:
> + case P10V_BUILTIN_MTVSRDM:
> + case P10V_BUILTIN_MTVSRQM:
> + case P10V_BUILTIN_VCNTMBB:
> + case P10V_BUILTIN_VCNTMBH:
> + case P10V_BUILTIN_VCNTMBW:
> + case P10V_BUILTIN_VCNTMBD:
> + case P10V_BUILTIN_VEXPANDMB:
> + case P10V_BUILTIN_VEXPANDMH:
> + case P10V_BUILTIN_VEXPANDMW:
> + case P10V_BUILTIN_VEXPANDMD:
> + case P10V_BUILTIN_VEXPANDMQ:
> h.uns_p[0] = 1;
> h.uns_p[1] = 1;
> break;
> @@ -14091,16 +14091,16 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
> case P8V_BUILTIN_ORC_V4SI_UNS:
> case P8V_BUILTIN_ORC_V2DI_UNS:
> case P8V_BUILTIN_ORC_V1TI_UNS:
> - case P10_BUILTIN_VCFUGED:
> - case P10_BUILTIN_VCLZDM:
> - case P10_BUILTIN_VCTZDM:
> - case P10_BUILTIN_VGNB:
> - case P10_BUILTIN_VPDEPD:
> - case P10_BUILTIN_VPEXTD:
> - case P10_BUILTIN_XXGENPCVM_V16QI:
> - case P10_BUILTIN_XXGENPCVM_V8HI:
> - case P10_BUILTIN_XXGENPCVM_V4SI:
> - case P10_BUILTIN_XXGENPCVM_V2DI:
> + case P10V_BUILTIN_VCFUGED:
> + case P10V_BUILTIN_VCLZDM:
> + case P10V_BUILTIN_VCTZDM:
> + case P10V_BUILTIN_VGNB:
> + case P10V_BUILTIN_VPDEPD:
> + case P10V_BUILTIN_VPEXTD:
> + case P10V_BUILTIN_XXGENPCVM_V16QI:
> + case P10V_BUILTIN_XXGENPCVM_V8HI:
> + case P10V_BUILTIN_XXGENPCVM_V4SI:
> + case P10V_BUILTIN_XXGENPCVM_V2DI:
> h.uns_p[0] = 1;
> h.uns_p[1] = 1;
> h.uns_p[2] = 1;
> @@ -14131,29 +14131,29 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
> case CRYPTO_BUILTIN_VSHASIGMAW:
> case CRYPTO_BUILTIN_VSHASIGMAD:
> case CRYPTO_BUILTIN_VSHASIGMA:
> - case P10_BUILTIN_VEXTRACTBL:
> - case P10_BUILTIN_VEXTRACTHL:
> - case P10_BUILTIN_VEXTRACTWL:
> - case P10_BUILTIN_VEXTRACTDL:
> - case P10_BUILTIN_VEXTRACTBR:
> - case P10_BUILTIN_VEXTRACTHR:
> - case P10_BUILTIN_VEXTRACTWR:
> - case P10_BUILTIN_VEXTRACTDR:
> - case P10_BUILTIN_VINSERTGPRBL:
> - case P10_BUILTIN_VINSERTGPRHL:
> - case P10_BUILTIN_VINSERTGPRWL:
> - case P10_BUILTIN_VINSERTGPRDL:
> - case P10_BUILTIN_VINSERTVPRBL:
> - case P10_BUILTIN_VINSERTVPRHL:
> - case P10_BUILTIN_VINSERTVPRWL:
> - case P10_BUILTIN_VREPLACE_ELT_UV4SI:
> - case P10_BUILTIN_VREPLACE_ELT_UV2DI:
> - case P10_BUILTIN_VREPLACE_UN_UV4SI:
> - case P10_BUILTIN_VREPLACE_UN_UV2DI:
> - case P10_BUILTIN_VXXBLEND_V16QI:
> - case P10_BUILTIN_VXXBLEND_V8HI:
> - case P10_BUILTIN_VXXBLEND_V4SI:
> - case P10_BUILTIN_VXXBLEND_V2DI:
> + case P10V_BUILTIN_VEXTRACTBL:
> + case P10V_BUILTIN_VEXTRACTHL:
> + case P10V_BUILTIN_VEXTRACTWL:
> + case P10V_BUILTIN_VEXTRACTDL:
> + case P10V_BUILTIN_VEXTRACTBR:
> + case P10V_BUILTIN_VEXTRACTHR:
> + case P10V_BUILTIN_VEXTRACTWR:
> + case P10V_BUILTIN_VEXTRACTDR:
> + case P10V_BUILTIN_VINSERTGPRBL:
> + case P10V_BUILTIN_VINSERTGPRHL:
> + case P10V_BUILTIN_VINSERTGPRWL:
> + case P10V_BUILTIN_VINSERTGPRDL:
> + case P10V_BUILTIN_VINSERTVPRBL:
> + case P10V_BUILTIN_VINSERTVPRHL:
> + case P10V_BUILTIN_VINSERTVPRWL:
> + case P10V_BUILTIN_VREPLACE_ELT_UV4SI:
> + case P10V_BUILTIN_VREPLACE_ELT_UV2DI:
> + case P10V_BUILTIN_VREPLACE_UN_UV4SI:
> + case P10V_BUILTIN_VREPLACE_UN_UV2DI:
> + case P10V_BUILTIN_VXXBLEND_V16QI:
> + case P10V_BUILTIN_VXXBLEND_V8HI:
> + case P10V_BUILTIN_VXXBLEND_V4SI:
> + case P10V_BUILTIN_VXXBLEND_V2DI:
> h.uns_p[0] = 1;
> h.uns_p[1] = 1;
> h.uns_p[2] = 1;
> @@ -14221,8 +14221,8 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
> case ALTIVEC_BUILTIN_VSRW:
> case P8V_BUILTIN_VSRD:
> /* Vector splat immediate insert */
> - case P10_BUILTIN_VXXSPLTI32DX_V4SI:
> - case P10_BUILTIN_VXXSPLTI32DX_V4SF:
> + case P10V_BUILTIN_VXXSPLTI32DX_V4SI:
> + case P10V_BUILTIN_VXXSPLTI32DX_V4SF:
> h.uns_p[2] = 1;
> break;
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
2020-08-13 18:38 ` Bill Schmidt
@ 2020-08-13 19:24 ` Carl Love
2020-08-13 19:48 ` Bill Schmidt
0 siblings, 1 reply; 20+ messages in thread
From: Carl Love @ 2020-08-13 19:24 UTC (permalink / raw)
To: wschmidt, Segher Boessenkool, dje.gcc, gcc-patches, Will Schmidt
Cc: Bill Schmidt, cel, Peter Bergner
Bill:
On Thu, 2020-08-13 at 13:38 -0500, Bill Schmidt wrote:
> Hi Carl,
>
> Thanks for cleaning up the consistency issue. The new names and
> related
> adjustments LGTM.
>
> Are there no affected test cases that need adjusting? That
> surprises
> me. For example, didn't __builtin_altivec_xxeval become
> __builtin_vsx_xxeval as a result of this change? Does that not
> appear
> in any test cases?
>
> Thanks,
>
> Bill
In gcc/config/rs6000/rs6000-builtin.def we have
#define vec_ternarylogic(a, b, c, d) __builtin_vec_xxeval (a, b, c, d)
The vec_ternarylogic() builtin is used in test files
gcc/testsuite/gcc.target/powerpc/vec-ternarylogic-X.c where X stands
for 1, 2, 3, 4, 5, 6, 7, 8, 9.
In gcc/confit/rs6000/rs6000-builtin.def
BU_P10V_VSX_4 (XXEVAL, "xxeval", CONST, xxeval)
now expands to __builtin_vsx_xxeval as you expect.
I do not see a test case that uses the old builtin name
__builtin_altivec_xxeval.
carll@genoa:~/GCC/gcc-mainline-935/gcc/testsuite/gcc.target/powerpc$
grep -r xxeval *
vec-ternarylogic-0.c:/* { dg-final { scan-assembler {\mxxeval\M} } } */
vec-ternarylogic-2.c:/* { dg-final { scan-assembler {\mxxeval\M} } } */
vec-ternarylogic-3.c:/* { dg-final { scan-assembler {\mxxeval\M} } } */
vec-ternarylogic-4.c:/* { dg-final { scan-assembler {\mxxeval\M} } } */
vec-ternarylogic-6.c:/* { dg-final { scan-assembler {\mxxeval\M} } } */
vec-ternarylogic-8.c:/* { dg-final { scan-assembler {\mxxeval\M} } } */
vec-ternarylogic-9.c:/* { dg-final { scan-assembler {\mxxeval\M} } } */
carll@genoa:~/GCC/gcc-mainline-935/gcc/testsuite/gcc.target/powerpc$
There just seems to be the various tests that are expected to generate
the xxeval instruction. As far as I can see there is no test program that uses the __builtin_altivec_xxeval name.
Carl
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
2020-08-13 19:24 ` Carl Love
@ 2020-08-13 19:48 ` Bill Schmidt
2020-08-13 20:00 ` Carl Love
0 siblings, 1 reply; 20+ messages in thread
From: Bill Schmidt @ 2020-08-13 19:48 UTC (permalink / raw)
To: Carl Love, Segher Boessenkool, dje.gcc, gcc-patches, Will Schmidt
Cc: Bill Schmidt, cel, Peter Bergner
On 8/13/20 2:24 PM, Carl Love wrote:
> Bill:
>
> On Thu, 2020-08-13 at 13:38 -0500, Bill Schmidt wrote:
>> Hi Carl,
>>
>> Thanks for cleaning up the consistency issue. The new names and
>> related
>> adjustments LGTM.
>>
>> Are there no affected test cases that need adjusting? That
>> surprises
>> me. For example, didn't __builtin_altivec_xxeval become
>> __builtin_vsx_xxeval as a result of this change? Does that not
>> appear
>> in any test cases?
>>
>> Thanks,
>>
>> Bill
> In gcc/config/rs6000/rs6000-builtin.def we have
>
> #define vec_ternarylogic(a, b, c, d) __builtin_vec_xxeval (a, b, c, d)
>
> The vec_ternarylogic() builtin is used in test files
> gcc/testsuite/gcc.target/powerpc/vec-ternarylogic-X.c where X stands
> for 1, 2, 3, 4, 5, 6, 7, 8, 9.
>
> In gcc/confit/rs6000/rs6000-builtin.def
>
> BU_P10V_VSX_4 (XXEVAL, "xxeval", CONST, xxeval)
>
> now expands to __builtin_vsx_xxeval as you expect.
>
> I do not see a test case that uses the old builtin name
> __builtin_altivec_xxeval.
>
> carll@genoa:~/GCC/gcc-mainline-935/gcc/testsuite/gcc.target/powerpc$
> grep -r xxeval *
> vec-ternarylogic-0.c:/* { dg-final { scan-assembler {\mxxeval\M} } } */
> vec-ternarylogic-2.c:/* { dg-final { scan-assembler {\mxxeval\M} } } */
> vec-ternarylogic-3.c:/* { dg-final { scan-assembler {\mxxeval\M} } } */
> vec-ternarylogic-4.c:/* { dg-final { scan-assembler {\mxxeval\M} } } */
> vec-ternarylogic-6.c:/* { dg-final { scan-assembler {\mxxeval\M} } } */
> vec-ternarylogic-8.c:/* { dg-final { scan-assembler {\mxxeval\M} } } */
> vec-ternarylogic-9.c:/* { dg-final { scan-assembler {\mxxeval\M} } } */
> carll@genoa:~/GCC/gcc-mainline-935/gcc/testsuite/gcc.target/powerpc$
>
> There just seems to be the various tests that are expected to generate
> the xxeval instruction. As far as I can see there is no test program that uses the __builtin_altivec_xxeval name.
OK, but that was just meant as an example. We have a fair number of
things that changed names, so I was somewhat surprised. It could be
that all of these are likewise hidden via the overload mechanism. Just
checking to be sure.
Thanks,
Bill
>
> Carl
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
2020-08-13 19:48 ` Bill Schmidt
@ 2020-08-13 20:00 ` Carl Love
2020-08-13 20:14 ` Peter Bergner
0 siblings, 1 reply; 20+ messages in thread
From: Carl Love @ 2020-08-13 20:00 UTC (permalink / raw)
To: wschmidt, Segher Boessenkool, dje.gcc, gcc-patches, Will Schmidt
Cc: Bill Schmidt, cel, Peter Bergner
Bill:
On Thu, 2020-08-13 at 14:48 -0500, Bill Schmidt wrote:
> OK, but that was just meant as an example. We have a fair number of
> things that changed names, so I was somewhat surprised. It could be
> that all of these are likewise hidden via the overload mechanism.
> Just
> checking to be sure.
OK, I will go dig thru the test cases in a similar way for all of the
changes just to make sure. I didn't get any test failures but yea, a
lot of changes so lets double check.
Carl
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
2020-08-13 20:00 ` Carl Love
@ 2020-08-13 20:14 ` Peter Bergner
0 siblings, 0 replies; 20+ messages in thread
From: Peter Bergner @ 2020-08-13 20:14 UTC (permalink / raw)
To: Carl Love
Cc: wschmidt, Segher Boessenkool, dje.gcc, gcc-patches, Will Schmidt, cel
On 8/13/20 3:00 PM, Carl Love wrote:
> On Thu, 2020-08-13 at 14:48 -0500, Bill Schmidt wrote:
>> OK, but that was just meant as an example. We have a fair number of
>> things that changed names, so I was somewhat surprised. It could be
>> that all of these are likewise hidden via the overload mechanism.
>> Just
>> checking to be sure.
>
> OK, I will go dig thru the test cases in a similar way for all of the
> changes just to make sure. I didn't get any test failures but yea, a
> lot of changes so lets double check.
I too was surprised there were no testsuite changes required.
If you ran the testsuite twice with the unpatched and patched
builds (as is required for patch submission) and there were no
regressions, then great. Wow, but great.
Peter
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
2020-08-13 16:12 [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions Carl Love
2020-08-13 18:38 ` Bill Schmidt
@ 2020-08-14 21:33 ` Segher Boessenkool
2020-08-14 22:32 ` Carl Love
1 sibling, 1 reply; 20+ messages in thread
From: Segher Boessenkool @ 2020-08-14 21:33 UTC (permalink / raw)
To: Carl Love
Cc: dje.gcc, gcc-patches, Will Schmidt, Bill Schmidt, cel, Peter Bergner
Hi Carl,
On Thu, Aug 13, 2020 at 09:12:48AM -0700, Carl Love wrote:
> The macro expansion for the bfloat convert intrinsics XVCVBF16SP and
> XVCVSPBF16 need to be restricted to P10.
> The following patch creates new macro expansions BU_P10V_VSX_# and
> BU_P10V_AV_# for the VSX and Altivec instructions respectively. The
> new names are consistent with the P8 and P9 naming convention for the
> VSX and Altivec instructions.
So _vsx if it is for all VSRs, but _altivec for just the VRs?
> The macro expansion for XVCVBF16SP and XVCVSPBF16 is changed from
> BU_VSX_1 to BU_P10V_VSX_1 to restrict it to P10 and beyond. Also MISC
> is changed to CONST in the macro expansion call.
The spelling of the xvcvbf16sp name will probably change, fwiw. So you
might want to wait before committing this (but changing it later is fine
as well).
> The side effect of creating the macro expansions for VSX and Altivec is
> it changes all of the expanded names. The patch fixes all the uses of
> the expanded names as needed for the new VSX and Altivec macros.
Joy :-)
Do the names agree with the (future) documentation now?
> -#define BU_P10V_1(ENUM, NAME, ATTR, ICODE) \
> - RS6000_BUILTIN_1 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
> - "__builtin_altivec_" NAME, /* NAME */ \
> +#define BU_P10V_VSX_1(ENUM, NAME, ATTR, ICODE) \
Hrm, this now says "V" (for vector) as well as "VSX" (for all 64 vector
regs allowed). One of those is superfluous.
> + RS6000_BUILTIN_1 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
So this enum name doesn't say it allows all 64 registers?
> + "__builtin_vsx_" NAME, /* NAME */ \
> /* Builtins for vector instructions added in ISA 3.1 (power10). */
> -BU_P10V_2 (VCLRLB, "vclrlb", CONST, vclrlb)
> +BU_P10V_AV_2 (VCLRLB, "vclrlb", CONST, vclrlb)
Maybe you should just keep "V" for insns using only the VRs (which you
call V_AV now), and do "VS" for those working on all VSRs (which you call
V_VSX here)?
Segher
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
2020-08-14 21:33 ` Segher Boessenkool
@ 2020-08-14 22:32 ` Carl Love
2020-08-15 0:42 ` Segher Boessenkool
0 siblings, 1 reply; 20+ messages in thread
From: Carl Love @ 2020-08-14 22:32 UTC (permalink / raw)
To: Segher Boessenkool
Cc: dje.gcc, gcc-patches, Will Schmidt, Bill Schmidt, cel, Peter Bergner
On Fri, 2020-08-14 at 16:33 -0500, Segher Boessenkool wrote:
> Hi Carl,
>
> On Thu, Aug 13, 2020 at 09:12:48AM -0700, Carl Love wrote:
> > The macro expansion for the bfloat convert intrinsics XVCVBF16SP
> > and
> > XVCVSPBF16 need to be restricted to P10.
> > The following patch creates new macro expansions BU_P10V_VSX_# and
> > BU_P10V_AV_# for the VSX and Altivec instructions
> > respectively. The
> > new names are consistent with the P8 and P9 naming convention for
> > the
> > VSX and Altivec instructions.
>
> So _vsx if it is for all VSRs, but _altivec for just the VRs?
Yes, I worked off the rule that Altivec registers are designated with
5-bits and VSR registers are designated with 6-bits.
>
> > The macro expansion for XVCVBF16SP and XVCVSPBF16 is changed from
> > BU_VSX_1 to BU_P10V_VSX_1 to restrict it to P10 and beyond. Also
> > MISC
> > is changed to CONST in the macro expansion call.
>
> The spelling of the xvcvbf16sp name will probably change, fwiw. So
> you
> might want to wait before committing this (but changing it later is
> fine
> as well).
OK, not sure of the urgency to get this patch in. Bill noted the error
recently in the expansion. Will check with him to see if we should
wait and go with the new name or go with the old name for now.
<snip>
>
> Do the names agree with the (future) documentation now?
Did not double check on the documentation.
>
> > -#define BU_P10V_1(ENUM, NAME, ATTR, ICODE)
> > \
> > - RS6000_BUILTIN_1 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
> > - "__builtin_altivec_" NAME, /* NAME */
> > \
> > +#define BU_P10V_VSX_1(ENUM, NAME, ATTR, ICODE)
> > \
>
> Hrm, this now says "V" (for vector) as well as "VSX" (for all 64
> vector
> regs allowed). One of those is superfluous.
>
> > + RS6000_BUILTIN_1 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
>
> So this enum name doesn't say it allows all 64 registers?
>
> > + "__builtin_vsx_" NAME, /* NAME */ \
>
>
> > /* Builtins for vector instructions added in ISA 3.1
> > (power10). */
> > -BU_P10V_2 (VCLRLB, "vclrlb", CONST, vclrlb)
> > +BU_P10V_AV_2 (VCLRLB, "vclrlb", CONST, vclrlb)
>
> Maybe you should just keep "V" for insns using only the VRs (which
> you
> call V_AV now), and do "VS" for those working on all VSRs (which you
> call
> V_VSX here)?
The names BU_P10V_AV_# and BU_P10V_VSX_# were used for consistency with
the Power 8 and Power 9 naming, per my discussion with Peter. The
following already exist in rs6000-builtin.def for similar uses.
#define BU_P8V_AV_1(ENUM, NAME, ATTR, ICODE)
#define BU_P8V_AV_2(ENUM, NAME, ATTR, ICODE)
#define BU_P8V_AV_3(ENUM, NAME, ATTR, ICODE)
#define BU_P9V_AV_1(ENUM, NAME, ATTR, ICODE)
#define BU_P9V_AV_2(ENUM, NAME, ATTR, ICODE)
#define BU_P9V_AV_3(ENUM, NAME, ATTR, ICODE)
#define BU_P8V_VSX_1(ENUM, NAME, ATTR, ICODE)
#define BU_P8V_VSX_2(ENUM, NAME, ATTR, ICODE)
#define BU_P9V_VSX_1(ENUM, NAME, ATTR, ICODE)
#define BU_P9V_VSX_2(ENUM, NAME, ATTR, ICODE)
#define BU_P9V_VSX_3(ENUM, NAME, ATTR, ICODE)
I agree the V seems redundant given the VSX, AV in the name.
The overload macros:
#define BU_P8V_OVERLOAD_1(ENUM, NAME)
#define BU_P8V_OVERLOAD_2(ENUM, NAME)
#define BU_P8V_OVERLOAD_3(ENUM, NAME)
#define BU_P9_OVERLOAD_2(ENUM, NAME)
#define BU_P9V_OVERLOAD_1(ENUM, NAME)
#define BU_P9V_OVERLOAD_2(ENUM, NAME)
#define BU_P9V_OVERLOAD_3(ENUM, NAME)
Looks like BU_P9_OVERLOAD_2 and BU_P9V_OVERLOAD_2 are identical
definitions. That should probably be fixed.....
Seems like you need V in the processor name for the OVERLOAD
definitions to make it clear they are vector definitions. I don't
believe the OVERLOAD cares if the builtin is for vsx or altivec
registers. It kinda makes sense to leave the V in BU_P8V_VSX_#,
BU_P9V_VSX_#, BU_P8V_AV_#, BU_P9V_AV_# definitions for consistency with
the OVERLOAD macro name? Thoughts? I will change to whatever everyone
agrees on.
Carl
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
2020-08-14 22:32 ` Carl Love
@ 2020-08-15 0:42 ` Segher Boessenkool
2020-08-17 17:13 ` Carl Love
2020-08-19 19:19 ` [EXTERNAL] " Peter Bergner
0 siblings, 2 replies; 20+ messages in thread
From: Segher Boessenkool @ 2020-08-15 0:42 UTC (permalink / raw)
To: Carl Love
Cc: dje.gcc, gcc-patches, Will Schmidt, Bill Schmidt, cel, Peter Bergner
Hi!
On Fri, Aug 14, 2020 at 03:32:47PM -0700, Carl Love wrote:
> On Fri, 2020-08-14 at 16:33 -0500, Segher Boessenkool wrote:
> > So _vsx if it is for all VSRs, but _altivec for just the VRs?
>
> Yes, I worked off the rule that Altivec registers are designated with
> 5-bits and VSR registers are designated with 6-bits.
Excellent :-)
> > Do the names agree with the (future) documentation now?
>
> Did not double check on the documentation.
Someone should...
> > > -#define BU_P10V_1(ENUM, NAME, ATTR, ICODE)
> > > \
> > > - RS6000_BUILTIN_1 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
> > > - "__builtin_altivec_" NAME, /* NAME */
> > > \
> > > +#define BU_P10V_VSX_1(ENUM, NAME, ATTR, ICODE)
> > > \
> >
> > Hrm, this now says "V" (for vector) as well as "VSX" (for all 64
> > vector
> > regs allowed). One of those is superfluous.
> >
> > > + RS6000_BUILTIN_1 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
> >
> > So this enum name doesn't say it allows all 64 registers?
> >
> > > + "__builtin_vsx_" NAME, /* NAME */ \
> >
> >
> > > /* Builtins for vector instructions added in ISA 3.1
> > > (power10). */
> > > -BU_P10V_2 (VCLRLB, "vclrlb", CONST, vclrlb)
> > > +BU_P10V_AV_2 (VCLRLB, "vclrlb", CONST, vclrlb)
> >
> > Maybe you should just keep "V" for insns using only the VRs (which
> > you
> > call V_AV now), and do "VS" for those working on all VSRs (which you
> > call
> > V_VSX here)?
>
> The names BU_P10V_AV_# and BU_P10V_VSX_# were used for consistency with
> the Power 8 and Power 9 naming, per my discussion with Peter.
Ah, okay, yes let's keep it all consistent then, to make the rewrite
easier :-)
> The overload macros:
>
> #define BU_P8V_OVERLOAD_1(ENUM, NAME)
> #define BU_P8V_OVERLOAD_2(ENUM, NAME)
> #define BU_P8V_OVERLOAD_3(ENUM, NAME)
>
> #define BU_P9_OVERLOAD_2(ENUM, NAME)
>
> #define BU_P9V_OVERLOAD_1(ENUM, NAME)
> #define BU_P9V_OVERLOAD_2(ENUM, NAME)
> #define BU_P9V_OVERLOAD_3(ENUM, NAME)
>
> Looks like BU_P9_OVERLOAD_2 and BU_P9V_OVERLOAD_2 are identical
> definitions. That should probably be fixed.....
It's __builtin_ vs. __builtin_vec_.
> Thoughts? I will change to whatever everyone agrees on.
I think your current code is fine; I hadn't considered Bill's upcoming
rewrite. It is more important to make that go smoother than to fix some
aesthetics right now.
Please check if the names for the builtins match the (future)
documentation, and then, approved for trunk. Thank you!
Segher
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
2020-08-15 0:42 ` Segher Boessenkool
@ 2020-08-17 17:13 ` Carl Love
2020-08-17 18:09 ` [EXTERNAL] " Bill Schmidt
2020-08-19 19:19 ` [EXTERNAL] " Peter Bergner
1 sibling, 1 reply; 20+ messages in thread
From: Carl Love @ 2020-08-17 17:13 UTC (permalink / raw)
To: Segher Boessenkool
Cc: dje.gcc, gcc-patches, Will Schmidt, Bill Schmidt, cel, Peter Bergner
Segher, Bill, Peter:
On Fri, 2020-08-14 at 19:42 -0500, Segher Boessenkool wrote:
> > > Do the names agree with the (future) documentation now?
> >
> > Did not double check on the documentation.
>
> Someone should...
Looking at the box document "Proposed function Prototypes for P10".
There are a number of builtins of the form "name()" which get expanded
to
__builtin_altivec_name or __builtin_vsx_name.
But there does not appear to be any additional defined prototype for
the __builtin_altivec_name or __builtin_vsx_name in the document so we
don't need to worry about these prototypes as far as I can see.
There are three prototypes __builtin_cfuged, __builtin_pdepd,
__builtin_pextd defined in the document.
The corresponding builtin definitions in GCC are:
__builtin_altivec_cfuged, __builtin_altivec_pdepd,
__builtin_altivec_pextd
which does not match the defined prototype in the document.
I don't see any defines in gcc/config/rs6000 that would map
__builtin_name to __builtin_altivec_name so these three appear to be
unsupported as far as I can see. I assume adding
#define __builtin_name __builtin_altivec_name
to gcc/config/rs6000/altivec.h would be the easiest way to define the
prototypes from the document. I can add the defines if you think that
is the correct fix. Please let me know.
The MMA related builtins at the end of the document appear to have the
proper define BU_MMA_# macro expansions to generate the defined
prototype names.
Looking at the builtin definitions in box for RFC 2608, RFC 2609, RFC
2629 the builtins are all of the form name() so I don't see any issues
with the internal GCC name changes for the builtins in these documents.
Carl
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [EXTERNAL] Re: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
2020-08-17 17:13 ` Carl Love
@ 2020-08-17 18:09 ` Bill Schmidt
2020-08-17 18:25 ` Carl Love
0 siblings, 1 reply; 20+ messages in thread
From: Bill Schmidt @ 2020-08-17 18:09 UTC (permalink / raw)
To: Carl Love, Segher Boessenkool
Cc: dje.gcc, gcc-patches, Will Schmidt, Bill Schmidt, cel, Peter Bergner
On 8/17/20 12:13 PM, Carl Love wrote:
> Segher, Bill, Peter:
>
> On Fri, 2020-08-14 at 19:42 -0500, Segher Boessenkool wrote:
>>>> Do the names agree with the (future) documentation now?
>>> Did not double check on the documentation.
>> Someone should...
> Looking at the box document "Proposed function Prototypes for P10".
>
> There are a number of builtins of the form "name()" which get expanded
> to
>
> __builtin_altivec_name or __builtin_vsx_name.
>
> But there does not appear to be any additional defined prototype for
> the __builtin_altivec_name or __builtin_vsx_name in the document so we
> don't need to worry about these prototypes as far as I can see.
>
>
> There are three prototypes __builtin_cfuged, __builtin_pdepd,
> __builtin_pextd defined in the document.
>
> The corresponding builtin definitions in GCC are:
>
> __builtin_altivec_cfuged, __builtin_altivec_pdepd,
> __builtin_altivec_pextd
>
> which does not match the defined prototype in the document.
These are scalar instructions, not vector, so they should not be using
any flavor of "V". They should be using BU_P10_MISC_n, where n is the
number of arguments.
Bill
>
> I don't see any defines in gcc/config/rs6000 that would map
> __builtin_name to __builtin_altivec_name so these three appear to be
> unsupported as far as I can see. I assume adding
>
> #define __builtin_name __builtin_altivec_name
>
> to gcc/config/rs6000/altivec.h would be the easiest way to define the
> prototypes from the document. I can add the defines if you think that
> is the correct fix. Please let me know.
>
>
> The MMA related builtins at the end of the document appear to have the
> proper define BU_MMA_# macro expansions to generate the defined
> prototype names.
>
>
> Looking at the builtin definitions in box for RFC 2608, RFC 2609, RFC
> 2629 the builtins are all of the form name() so I don't see any issues
> with the internal GCC name changes for the builtins in these documents.
>
> Carl
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
2020-08-17 18:09 ` [EXTERNAL] " Bill Schmidt
@ 2020-08-17 18:25 ` Carl Love
0 siblings, 0 replies; 20+ messages in thread
From: Carl Love @ 2020-08-17 18:25 UTC (permalink / raw)
To: wschmidt, Segher Boessenkool
Cc: dje.gcc, gcc-patches, Will Schmidt, Bill Schmidt, cel, Peter Bergner
Bill:
On Mon, 2020-08-17 at 13:09 -0500, Bill Schmidt wrote:
> >
> > There are three prototypes __builtin_cfuged, __builtin_pdepd,
> > __builtin_pextd defined in the document.
> >
> > The corresponding builtin definitions in GCC are:
> >
> > __builtin_altivec_cfuged, __builtin_altivec_pdepd,
> > __builtin_altivec_pextd
> >
> > which does not match the defined prototype in the document.
>
>
> These are scalar instructions, not vector, so they should not be
> using
> any flavor of "V". They should be using BU_P10_MISC_n, where n is
> the
> number of arguments.
Yes, looks like that is those are the scalar versions. I got them
mixed up with the vector definitions
vector unsigned long long int vec_pdep()
vector unsigned long long int vec_pext ()
vector unsigned long long int vec_cfuge ()
I was thinking the __builtin_name() was also referring to the vector
versions.
So, given that there are separate definitions, it does appear that the
names are all consistent with the documentation. Thanks Bill.
Carl
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [EXTERNAL] Re: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
2020-08-15 0:42 ` Segher Boessenkool
2020-08-17 17:13 ` Carl Love
@ 2020-08-19 19:19 ` Peter Bergner
2020-08-19 20:16 ` Segher Boessenkool
1 sibling, 1 reply; 20+ messages in thread
From: Peter Bergner @ 2020-08-19 19:19 UTC (permalink / raw)
To: Segher Boessenkool
Cc: Carl Love, dje.gcc, gcc-patches, Will Schmidt, Bill Schmidt, cel
On 8/14/20 7:42 PM, Segher Boessenkool wrote:
> I think your current code is fine; I hadn't considered Bill's upcoming
> rewrite. It is more important to make that go smoother than to fix some
> aesthetics right now.
>
> Please check if the names for the builtins match the (future)
> documentation, and then, approved for trunk. Thank you!
This is also a bug in GCC 10, so this should be backported too.
Segher, is this ok for Carl to backport to GCC 10 after it has sat on
trunk for a few days?
Peter
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [EXTERNAL] Re: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
2020-08-19 19:19 ` [EXTERNAL] " Peter Bergner
@ 2020-08-19 20:16 ` Segher Boessenkool
2020-08-19 23:34 ` Carl Love
2020-08-24 21:39 ` Carl Love
0 siblings, 2 replies; 20+ messages in thread
From: Segher Boessenkool @ 2020-08-19 20:16 UTC (permalink / raw)
To: Peter Bergner
Cc: Carl Love, dje.gcc, gcc-patches, Will Schmidt, Bill Schmidt, cel
On Wed, Aug 19, 2020 at 02:19:12PM -0500, Peter Bergner wrote:
> On 8/14/20 7:42 PM, Segher Boessenkool wrote:
> > I think your current code is fine; I hadn't considered Bill's upcoming
> > rewrite. It is more important to make that go smoother than to fix some
> > aesthetics right now.
> >
> > Please check if the names for the builtins match the (future)
> > documentation, and then, approved for trunk. Thank you!
>
> This is also a bug in GCC 10, so this should be backported too.
>
> Segher, is this ok for Carl to backport to GCC 10 after it has sat on
> trunk for a few days?
Yes. Thanks guys.
Segher
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
2020-08-19 20:16 ` Segher Boessenkool
@ 2020-08-19 23:34 ` Carl Love
2020-08-24 21:39 ` Carl Love
1 sibling, 0 replies; 20+ messages in thread
From: Carl Love @ 2020-08-19 23:34 UTC (permalink / raw)
To: Segher Boessenkool, Peter Bergner
Cc: dje.gcc, gcc-patches, Will Schmidt, Bill Schmidt, cel
On Wed, 2020-08-19 at 15:16 -0500, Segher Boessenkool wrote:
> On Wed, Aug 19, 2020 at 02:19:12PM -0500, Peter Bergner wrote:
> > On 8/14/20 7:42 PM, Segher Boessenkool wrote:
> > > I think your current code is fine; I hadn't considered Bill's
> > > upcoming
> > > rewrite. It is more important to make that go smoother than to
> > > fix some
> > > aesthetics right now.
> > >
> > > Please check if the names for the builtins match the (future)
> > > documentation, and then, approved for trunk. Thank you!
> >
> > This is also a bug in GCC 10, so this should be backported too.
> >
> > Segher, is this ok for Carl to backport to GCC 10 after it has sat
> > on
> > trunk for a few days?
>
> Yes. Thanks guys.
The patch was committed today, I left issue 935 open for the moment. I
will work on a backport patch for GCC 10 and then as long as nothing
bad happens I will push the patch early next week.
Carl
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
2020-08-19 20:16 ` Segher Boessenkool
2020-08-19 23:34 ` Carl Love
@ 2020-08-24 21:39 ` Carl Love
2020-08-25 16:56 ` [EXTERNAL] " will schmidt
2020-08-26 20:46 ` Segher Boessenkool
1 sibling, 2 replies; 20+ messages in thread
From: Carl Love @ 2020-08-24 21:39 UTC (permalink / raw)
To: Segher Boessenkool, Peter Bergner
Cc: dje.gcc, gcc-patches, Will Schmidt, Bill Schmidt, cel
Segher:
On Wed, 2020-08-19 at 15:16 -0500, Segher Boessenkool wrote:
> On Wed, Aug 19, 2020 at 02:19:12PM -0500, Peter Bergner wrote:
> > On 8/14/20 7:42 PM, Segher Boessenkool wrote:
> > > I think your current code is fine; I hadn't considered Bill's
> > > upcoming
> > > rewrite. It is more important to make that go smoother than to
> > > fix some
> > > aesthetics right now.
> > >
> > > Please check if the names for the builtins match the (future)
> > > documentation, and then, approved for trunk. Thank you!
> >
> > This is also a bug in GCC 10, so this should be backported too.
> >
> > Segher, is this ok for Carl to backport to GCC 10 after it has sat
> > on
> > trunk for a few days?
>
> Yes. Thanks guys.
I attempted to do the backport however the patch doesn't even come
close to applying. The names XVCVBF16SPN and XVCVSPBF16 are the only
two builtin names that exist in GCC 10. The other issue is there is no
Power 10 builtin macro definitions in GCC 10. So basically, I can fix
the issue with XVCVBF16SPN and XVCVSPBF16 to be restricted to Power 10
by adding the needed Power 10 macro definition.
This is a whole new patch so I figure it needs to be reviewed to make
sure we want to make this change to GCC 10. I did run the regression
tests again using a Power 9 machine to verify it complies and there are
no regression test failures.
Please let me know if this is OK for the GCC 10 tree. Thanks.
Carl Love
------------------------------------------------------------
[PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Back port to GCC 10.
gcc/ChangeLog
2020-08-24 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000-builtin.def: (BU_P10V_VSX_1) New builtin macro expansion.
(XVCVBF16SPN, XVCVSPBF16): Replace macro expansion BU_VSX_1 with BU_P10V_VSX_1.
* config/rs6000/rs6000-call.c: (VSX_BUILTIN_XVCVSPBF16, VSX_BUILTIN_XVCVBF16SPN):
Replace with P10V_BUILTIN_XVCVSPBF16, P10V_BUILTIN_XVCVBF16SPN respectively.
---
gcc/config/rs6000/rs6000-builtin.def | 14 ++++++++++++--
gcc/config/rs6000/rs6000-call.c | 4 ++--
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index 88f78cb0a15..512b7629a46 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1014,6 +1014,16 @@
| RS6000_BTC_BINARY), \
CODE_FOR_ ## ICODE) /* ICODE */
+/* For builtins for power10 vector instructions that are encoded as altivec
+ instructions, use __builtin_altivec_ as the builtin name. */
+
+#define BU_P10V_VSX_1(ENUM, NAME, ATTR, ICODE)\
+ RS6000_BUILTIN_1 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
+ "__builtin_vsx_" NAME, /* NAME */ \
+ RS6000_BTM_P10, /* MASK */ \
+ (RS6000_BTC_ ## ATTR /* ATTR */ \
+ | RS6000_BTC_UNARY), \
+ CODE_FOR_ ## ICODE) /* ICODE */
#endif
\f
@@ -2698,8 +2708,8 @@ BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS,
RS6000_BTC_MISC)
/* POWER10 MMA builtins. */
-BU_VSX_1 (XVCVBF16SPN, "xvcvbf16spn", MISC, vsx_xvcvbf16spn)
-BU_VSX_1 (XVCVSPBF16, "xvcvspbf16", MISC, vsx_xvcvspbf16)
+BU_P10V_VSX_1 (XVCVBF16SPN, "xvcvbf16spn", MISC, vsx_xvcvbf16spn)
+BU_P10V_VSX_1 (XVCVSPBF16, "xvcvspbf16", MISC, vsx_xvcvspbf16)
BU_MMA_1 (XXMFACC, "xxmfacc", QUAD, mma_xxmfacc)
BU_MMA_1 (XXMTACC, "xxmtacc", QUAD, mma_xxmtacc)
diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
index 2cf78dfa5fe..fc1671e1bb2 100644
--- a/gcc/config/rs6000/rs6000-call.c
+++ b/gcc/config/rs6000/rs6000-call.c
@@ -13383,8 +13383,8 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
case P8V_BUILTIN_VGBBD:
case MISC_BUILTIN_CDTBCD:
case MISC_BUILTIN_CBCDTD:
- case VSX_BUILTIN_XVCVSPBF16:
- case VSX_BUILTIN_XVCVBF16SPN:
+ case P10V_BUILTIN_XVCVSPBF16:
+ case P10V_BUILTIN_XVCVBF16SPN:
h.uns_p[0] = 1;
h.uns_p[1] = 1;
break;
--
2.17.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [EXTERNAL] Re: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
2020-08-24 21:39 ` Carl Love
@ 2020-08-25 16:56 ` will schmidt
2020-08-27 15:43 ` Carl Love
2020-08-26 20:46 ` Segher Boessenkool
1 sibling, 1 reply; 20+ messages in thread
From: will schmidt @ 2020-08-25 16:56 UTC (permalink / raw)
To: Carl Love, Segher Boessenkool, Peter Bergner
Cc: dje.gcc, gcc-patches, Bill Schmidt
On Mon, 2020-08-24 at 14:39 -0700, Carl Love wrote:
> Segher:
>
> On Wed, 2020-08-19 at 15:16 -0500, Segher Boessenkool wrote:
> > On Wed, Aug 19, 2020 at 02:19:12PM -0500, Peter Bergner wrote:
> > > On 8/14/20 7:42 PM, Segher Boessenkool wrote:
> > > > I think your current code is fine; I hadn't considered Bill's
> > > > upcoming
> > > > rewrite. It is more important to make that go smoother than to
> > > > fix some
> > > > aesthetics right now.
> > > >
> > > > Please check if the names for the builtins match the (future)
> > > > documentation, and then, approved for trunk. Thank you!
> > >
> > > This is also a bug in GCC 10, so this should be backported too.
> > >
> > > Segher, is this ok for Carl to backport to GCC 10 after it has sat
> > > on
> > > trunk for a few days?
> >
> > Yes. Thanks guys.
Hi,
>
> I attempted to do the backport however the patch doesn't even come
> close to applying. The names XVCVBF16SPN and XVCVSPBF16 are the only
> two builtin names that exist in GCC 10. The other issue is there is no
> Power 10 builtin macro definitions in GCC 10. So basically, I can fix
> the issue with XVCVBF16SPN and XVCVSPBF16 to be restricted to Power 10
> by adding the needed Power 10 macro definition.
>
> This is a whole new patch so I figure it needs to be reviewed to make
> sure we want to make this change to GCC 10. I did run the regression
> tests again using a Power 9 machine to verify it complies and there are
> no regression test failures.
>
I recommend a pure and clean description of what the patch is doing in a paragraph, separate from the history.
"
This patch corrects the built-in definitions for cvcvspbf16 and xvcvbf16spn to restrict their use to P10 and beyond in a way that
is consistent with the P8 and P9 builtin naming conventions.
This is a subset of changes made to trunk ...
"
> Please let me know if this is OK for the GCC 10 tree. Thanks.
>
> Carl Love
>
> ------------------------------------------------------------
> [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Back port to GCC 10.
>
> gcc/ChangeLog
>
> 2020-08-24 Carl Love <cel@us.ibm.com>
whitespace/indentation
> * config/rs6000/rs6000-builtin.def: (BU_P10V_VSX_1) New builtin macro expansion.
> (XVCVBF16SPN, XVCVSPBF16): Replace macro expansion BU_VSX_1 with BU_P10V_VSX_1.
OK as long as it's clear 'replace' means the define being used, versus the macro expansions themselves being replaced.
> * config/rs6000/rs6000-call.c: (VSX_BUILTIN_XVCVSPBF16, VSX_BUILTIN_XVCVBF16SPN):
> Replace with P10V_BUILTIN_XVCVSPBF16, P10V_BUILTIN_XVCVBF16SPN respectively.
s/Replace with/Rename to/ ?
> ---
> gcc/config/rs6000/rs6000-builtin.def | 14 ++++++++++++--
> gcc/config/rs6000/rs6000-call.c | 4 ++--
> 2 files changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
> index 88f78cb0a15..512b7629a46 100644
> --- a/gcc/config/rs6000/rs6000-builtin.def
> +++ b/gcc/config/rs6000/rs6000-builtin.def
> @@ -1014,6 +1014,16 @@
> | RS6000_BTC_BINARY), \
> CODE_FOR_ ## ICODE) /* ICODE */
>
> +/* For builtins for power10 vector instructions that are encoded as altivec
> + instructions, use __builtin_altivec_ as the builtin name. */
That comment doesn't seem to apply to this change, update or drop ?
> +
> +#define BU_P10V_VSX_1(ENUM, NAME, ATTR, ICODE)\
> + RS6000_BUILTIN_1 (P10_BUILTIN_ ## ENUM, /* ENUM */ \
> + "__builtin_vsx_" NAME, /* NAME */ \
> + RS6000_BTM_P10, /* MASK */ \
> + (RS6000_BTC_ ## ATTR /* ATTR */ \
> + | RS6000_BTC_UNARY), \
> + CODE_FOR_ ## ICODE) /* ICODE */
> #endif
>
>
> @@ -2698,8 +2708,8 @@ BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS,
> RS6000_BTC_MISC)
>
> /* POWER10 MMA builtins. */
> -BU_VSX_1 (XVCVBF16SPN, "xvcvbf16spn", MISC, vsx_xvcvbf16spn)
> -BU_VSX_1 (XVCVSPBF16, "xvcvspbf16", MISC, vsx_xvcvspbf16)
> +BU_P10V_VSX_1 (XVCVBF16SPN, "xvcvbf16spn", MISC, vsx_xvcvbf16spn)
> +BU_P10V_VSX_1 (XVCVSPBF16, "xvcvspbf16", MISC, vsx_xvcvspbf16)
>
> BU_MMA_1 (XXMFACC, "xxmfacc", QUAD, mma_xxmfacc)
> BU_MMA_1 (XXMTACC, "xxmtacc", QUAD, mma_xxmtacc)
> diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
> index 2cf78dfa5fe..fc1671e1bb2 100644
> --- a/gcc/config/rs6000/rs6000-call.c
> +++ b/gcc/config/rs6000/rs6000-call.c
> @@ -13383,8 +13383,8 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
> case P8V_BUILTIN_VGBBD:
> case MISC_BUILTIN_CDTBCD:
> case MISC_BUILTIN_CBCDTD:
> - case VSX_BUILTIN_XVCVSPBF16:
> - case VSX_BUILTIN_XVCVBF16SPN:
> + case P10V_BUILTIN_XVCVSPBF16:
> + case P10V_BUILTIN_XVCVBF16SPN:
> h.uns_p[0] = 1;
> h.uns_p[1] = 1;
> break;
ok.
thanks,
-WIll
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
2020-08-24 21:39 ` Carl Love
2020-08-25 16:56 ` [EXTERNAL] " will schmidt
@ 2020-08-26 20:46 ` Segher Boessenkool
1 sibling, 0 replies; 20+ messages in thread
From: Segher Boessenkool @ 2020-08-26 20:46 UTC (permalink / raw)
To: Carl Love; +Cc: Peter Bergner, dje.gcc, gcc-patches, Will Schmidt, Bill Schmidt
Hi!
(All that Will says included by reference ;-) )
On Mon, Aug 24, 2020 at 02:39:41PM -0700, Carl Love wrote:
> I attempted to do the backport however the patch doesn't even come
> close to applying. The names XVCVBF16SPN and XVCVSPBF16 are the only
> two builtin names that exist in GCC 10. The other issue is there is no
> Power 10 builtin macro definitions in GCC 10. So basically, I can fix
> the issue with XVCVBF16SPN and XVCVSPBF16 to be restricted to Power 10
> by adding the needed Power 10 macro definition.
Okay, that is what we should do I agree.
> This is a whole new patch so I figure it needs to be reviewed to make
> sure we want to make this change to GCC 10. I did run the regression
> tests again using a Power 9 machine to verify it complies and there are
> no regression test failures.
>
> Please let me know if this is OK for the GCC 10 tree. Thanks.
The patch looks fine. It now is impossible to write a correct
changelog for a backport like this, so I won't review that part.
Please make it clear that this is a partial backport in the commit
message (and commit of what ofc). Okay for trunk with that. Thanks!
Segher
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
2020-08-25 16:56 ` [EXTERNAL] " will schmidt
@ 2020-08-27 15:43 ` Carl Love
2020-08-27 18:34 ` Segher Boessenkool
0 siblings, 1 reply; 20+ messages in thread
From: Carl Love @ 2020-08-27 15:43 UTC (permalink / raw)
To: will schmidt, Segher Boessenkool, Peter Bergner
Cc: dje.gcc, gcc-patches, Bill Schmidt, cel
GCC maintainers:
The following patch has been updated based on the comments from Will
and Segher.
The patch is a subset of the mainline commit:
commit
07d456bb80a16405723c98c2ab74ccc2a5a23898
Author: Carl Love <carll@us.ibm.com>
Date: Mon Aug 10 19:37:41 2020
-0500
rs6000, restrict bfloat convert intrinsic to Power 10. Fix
BU_P10V macro definitions.
Only the changes from the mainline patch to restrict the bfloat convert
intrinsics (XVCVBF16SPN and XVCVSPBF16) to Power 10 are included in
this patch. This patch adds the BU_P10V_VSX_1 macro definition for
Power 10. The macro definition restricts the use of the named
intrinsics similarly to Power 8 and Power 9.
The changes for the BU_10V macro definitions from the mainline patch do
not apply to the GCC 10 branch as the macro definitions and uses do not
exist in the GCC 10 branch.
The patch has been updated per the comments above. It was rebased onto
the latest GCC 10 code base and retested on
powerpc64le-unknown-linux-gnu (Power 9 LE)
with no regressions. Please let me know if this patch is acceptable
for the GCC 10 branch. Thank you.
Carl Love
--------------------------------------------------------------------
rs6000, restrict bfloat convert intrinsic to Power 10.
gcc/ChangeLog
2020-08-26 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000-builtin.def: (BU_P10V_VSX_1) New builtin macro expansion.
(XVCVBF16SPN, XVCVSPBF16): Replace macro expansion BU_VSX_1 with BU_P10V_VSX_1.
* config/rs6000/rs6000-call.c: (VSX_BUILTIN_XVCVSPBF16, VSX_BUILTIN_XVCVBF16SPN):
Replace with P10V_BUILTIN_XVCVSPBF16, P10V_BUILTIN_XVCVBF16SPN respectively.
---
gcc/config/rs6000/rs6000-builtin.def | 12 ++++++++++--
gcc/config/rs6000/rs6000-call.c | 4 ++--
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index 88f78cb0a15..5de17e79855 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1014,6 +1014,14 @@
| RS6000_BTC_BINARY), \
CODE_FOR_ ## ICODE) /* ICODE */
+/* Built-ins for ISA 3.1 Altivec instructions. */
+#define BU_P10V_VSX_1(ENUM, NAME, ATTR, ICODE)\
+ RS6000_BUILTIN_1 (P10V_BUILTIN_ ## ENUM, /* ENUM */ \
+ "__builtin_vsx_" NAME, /* NAME */ \
+ RS6000_BTM_P10, /* MASK */ \
+ (RS6000_BTC_ ## ATTR /* ATTR */ \
+ | RS6000_BTC_UNARY), \
+ CODE_FOR_ ## ICODE) /* ICODE */
#endif
\f
@@ -2698,8 +2706,8 @@ BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS,
RS6000_BTC_MISC)
/* POWER10 MMA builtins. */
-BU_VSX_1 (XVCVBF16SPN, "xvcvbf16spn", MISC, vsx_xvcvbf16spn)
-BU_VSX_1 (XVCVSPBF16, "xvcvspbf16", MISC, vsx_xvcvspbf16)
+BU_P10V_VSX_1 (XVCVBF16SPN, "xvcvbf16spn", MISC, vsx_xvcvbf16spn)
+BU_P10V_VSX_1 (XVCVSPBF16, "xvcvspbf16", MISC, vsx_xvcvspbf16)
BU_MMA_1 (XXMFACC, "xxmfacc", QUAD, mma_xxmfacc)
BU_MMA_1 (XXMTACC, "xxmtacc", QUAD, mma_xxmtacc)
diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
index 2cf78dfa5fe..fc1671e1bb2 100644
--- a/gcc/config/rs6000/rs6000-call.c
+++ b/gcc/config/rs6000/rs6000-call.c
@@ -13383,8 +13383,8 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
case P8V_BUILTIN_VGBBD:
case MISC_BUILTIN_CDTBCD:
case MISC_BUILTIN_CBCDTD:
- case VSX_BUILTIN_XVCVSPBF16:
- case VSX_BUILTIN_XVCVBF16SPN:
+ case P10V_BUILTIN_XVCVSPBF16:
+ case P10V_BUILTIN_XVCVBF16SPN:
h.uns_p[0] = 1;
h.uns_p[1] = 1;
break;
--
2.17.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.
2020-08-27 15:43 ` Carl Love
@ 2020-08-27 18:34 ` Segher Boessenkool
0 siblings, 0 replies; 20+ messages in thread
From: Segher Boessenkool @ 2020-08-27 18:34 UTC (permalink / raw)
To: Carl Love; +Cc: will schmidt, Peter Bergner, dje.gcc, gcc-patches, Bill Schmidt
On Thu, Aug 27, 2020 at 08:43:40AM -0700, Carl Love wrote:
> 2020-08-26 Carl Love <cel@us.ibm.com>
> * config/rs6000/rs6000-builtin.def: (BU_P10V_VSX_1) New builtin macro expansion.
> (XVCVBF16SPN, XVCVSPBF16): Replace macro expansion BU_VSX_1 with BU_P10V_VSX_1.
> * config/rs6000/rs6000-call.c: (VSX_BUILTIN_XVCVSPBF16, VSX_BUILTIN_XVCVBF16SPN):
> Replace with P10V_BUILTIN_XVCVSPBF16, P10V_BUILTIN_XVCVBF16SPN respectively.
(lines too long)
This patch is fine for GCC 10. Thanks!
As an aside:
> - case VSX_BUILTIN_XVCVSPBF16:
> - case VSX_BUILTIN_XVCVBF16SPN:
> + case P10V_BUILTIN_XVCVSPBF16:
> + case P10V_BUILTIN_XVCVBF16SPN:
Having "P10V" in the name here doesn't really help anything; in fact, it
could just be BUILTIN_XVCBCVXBCXBNVC? Simpler names like that will
improve readability as well. But that is all for the future :-)
Segher
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2020-08-27 18:34 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-13 16:12 [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions Carl Love
2020-08-13 18:38 ` Bill Schmidt
2020-08-13 19:24 ` Carl Love
2020-08-13 19:48 ` Bill Schmidt
2020-08-13 20:00 ` Carl Love
2020-08-13 20:14 ` Peter Bergner
2020-08-14 21:33 ` Segher Boessenkool
2020-08-14 22:32 ` Carl Love
2020-08-15 0:42 ` Segher Boessenkool
2020-08-17 17:13 ` Carl Love
2020-08-17 18:09 ` [EXTERNAL] " Bill Schmidt
2020-08-17 18:25 ` Carl Love
2020-08-19 19:19 ` [EXTERNAL] " Peter Bergner
2020-08-19 20:16 ` Segher Boessenkool
2020-08-19 23:34 ` Carl Love
2020-08-24 21:39 ` Carl Love
2020-08-25 16:56 ` [EXTERNAL] " will schmidt
2020-08-27 15:43 ` Carl Love
2020-08-27 18:34 ` Segher Boessenkool
2020-08-26 20:46 ` Segher Boessenkool
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