From: Robin Dapp <rdapp.gcc@gmail.com>
To: Edwin Lu <ewlu@rivosinc.com>, gcc-patches@gcc.gnu.org
Cc: rdapp.gcc@gmail.com, gnu-toolchain@rivosinc.com
Subject: Re: [PATCH 1/2] RISC-V: Fix vwsll combine on rv32 targets
Date: Thu, 13 Jun 2024 16:43:20 +0200 [thread overview]
Message-ID: <f02c1d2f-5d26-44e3-ad50-84bc9cadf8b0@gmail.com> (raw)
In-Reply-To: <63e6639c-4fa6-4cb2-ab8e-ce437aa68d2f@rivosinc.com>
> I did a test run without the subreg condition and it also appears to
> work when running on rv32gcv and rv64gcv newlib. Would it be better
> to remove the subreg?
Yep, if it works, i.e. all tests still pass then let's get rid of it.
Regards
Robin
next prev parent reply other threads:[~2024-06-13 14:43 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-11 22:25 [PATCH 0/2] Fix ICE with vwsll combine on 32bit targets Edwin Lu
2024-06-11 22:25 ` [PATCH 1/2] RISC-V: Fix vwsll combine on rv32 targets Edwin Lu
2024-06-12 7:42 ` Robin Dapp
2024-06-12 20:19 ` Edwin Lu
2024-06-13 14:43 ` Robin Dapp [this message]
2024-06-11 22:25 ` [PATCH 2/2] RISC-V: Move mode assertion out of conditional branch in emit_insn Edwin Lu
2024-06-12 7:39 ` Robin Dapp
2024-06-12 20:25 ` Edwin Lu
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