Re: scheduler queue flush (was Re: [gcc-15 0/3] RISC-V improve stack/array access by constant mat tweak)

[Jeff Law <jeffreyalaw@gmail.com>]

On 3/21/24 11:19 AM, Vineet Gupta wrote:
> 

> 
> Oh yeah ! Robin hinted to this in Tues patchworks meeting too
> 
> default	    : 2,565,319,368,591
> 128	    : 2,509,741,035,068
> 256	    : 2,527,817,813,612
> no-sched{,2}: 1,295,520,567,376
So one more nugget here.  I happened to be doing some historical data 
mining and I can see the huge instruction jump in our internal runs.  We 
jump from 1.4T instructions to 2.1T.  But more importantly we see the 
cycle counts *improve* across that span, roughly 17%.   Unfortunately 
the data points are way far apart in time, so I don't think they help us 
narrow down the root cause.

Mostly it highlights that while instruction counts are generally 
correlated to cycle counts, they can deviate and in this case they do so 
wildly.  Whatever fix we end up making we'll likely need to run it on a 
design to evaluate its actual performance impact.

jeff