Hi,

Thank you very much for the modification, but I think we need to support 
la664 with the configuration items of configure.

I also defined ISA_BASE_LA64V110 to represent the LoongArch1.1 
instruction set, what do you think?


ÔÚ 2023/11/16 ÏÂÎç9:18, Xi Ruoyao дµÀ:
> Loongson 3A6000 processor will be shipped to general users in this month
> and it features 4 cores with the new LA664 micro architecture.  Here is
> some changes from LA464:
>
> 1. The 32-bit division instruction now ignores the high 32 bits of the
>     input registers.  This is enumerated via CPUCFG word 0x2, bit 26.
> 2. The micro architecture now guarantees two loads on the same memory
>     address won't be reordered with each other.  dbar 0x700 is turned
>     into nop.
> 3. The architecture now supports approximate square root instructions
>     (FRECIPE and VRSQRTE) on 32-bit or 64-bit floating-point values and
>     the vectors of these values.
> 4. The architecture now supports SC.Q instruction for 128-bit CAS.
> 5. The architecture now supports LL.ACQ and SC.REL instructions (well, I
>     don't really know what they are for).
> 6. The architecture now supports CAS instructions for 64, 32, 16, or 8-bit
>     values.
> 7. The architecture now supports atomic add and atomic swap instructions
>     for 16 or 8-bit values.
> 8. Some non-zero hint values of DBAR instructions are added.
>
> These features are documented in LoongArch v1.1.  Implementations can
> implement any subset of them and enumerate the implemented features via
> CPUCFG.  LA664 implements them all.
>
> (8) is already implemented in previous patches because it's completely
> backward-compatible.  This series implements (1) and (2) with switches
> -mdiv32 and -mld-seq-sa (these names are derived from the names of the
> corresponding CPUCFG bits documented in the LoongArch v1.1
> specification).
>
> The other features require Binutils support and we are close to the end
> of GCC 14 stage 1, so I'm posting this series first now.
>
> With -march=la664, these two options are implicitly enabled but they can
> be turned off with -mno-div32 or -mno-ld-seq-sa.
>
> With -march=native, the current CPU is probed via CPUCFG and these
> options are implicitly enabled if the CPU supports the corresponding
> feature.  They can be turned off with explicit -mno-div32 or
> -mno-ld-seq-sa as well.
>
> -mtune=la664 is implemented as a copy of -mtune=la464 and we can adjust
> it with benchmark results later.
>
> Bootstrapped and regtested on a LA664 with BOOT_CFLAGS="-march=la664
> -O2", a LA464 with BOOT_CFLAGS="-march=native -O2".  And manually
> verified -march=native probing on LA664 and LA464.
>
> Xi Ruoyao (5):
>    LoongArch: Switch loongarch-def to C++
>    LoongArch: genopts: Add infrastructure to generate code for new
>      features in ISA evolution
>    LoongArch: Take the advantage of -mdiv32 if it's enabled
>    LoongArch: Don't emit dbar 0x700 if -mld-seq-sa
>    LoongArch: Add -march=la664 and -mtune=la664
>
>   gcc/config/loongarch/genopts/genstr.sh        |  78 ++++++-
>   gcc/config/loongarch/genopts/isa-evolution.in |   2 +
>   .../loongarch/genopts/loongarch-strings       |   1 +
>   gcc/config/loongarch/genopts/loongarch.opt.in |  10 +
>   gcc/config/loongarch/loongarch-cpu.cc         |  37 ++--
>   gcc/config/loongarch/loongarch-cpucfg-map.h   |  36 +++
>   gcc/config/loongarch/loongarch-def-array.h    |  40 ++++
>   gcc/config/loongarch/loongarch-def.c          | 205 ------------------
>   gcc/config/loongarch/loongarch-def.cc         | 193 +++++++++++++++++
>   gcc/config/loongarch/loongarch-def.h          |  67 ++++--
>   gcc/config/loongarch/loongarch-opts.h         |   9 +-
>   gcc/config/loongarch/loongarch-str.h          |   8 +-
>   gcc/config/loongarch/loongarch-tune.h         | 123 ++++++++++-
>   gcc/config/loongarch/loongarch.cc             |   6 +-
>   gcc/config/loongarch/loongarch.md             |  31 ++-
>   gcc/config/loongarch/loongarch.opt            |  23 +-
>   gcc/config/loongarch/t-loongarch              |  25 ++-
>   .../gcc.target/loongarch/div-div32.c          |  31 +++
>   .../gcc.target/loongarch/div-no-div32.c       |  11 +
>   19 files changed, 664 insertions(+), 272 deletions(-)
>   create mode 100644 gcc/config/loongarch/genopts/isa-evolution.in
>   create mode 100644 gcc/config/loongarch/loongarch-cpucfg-map.h
>   create mode 100644 gcc/config/loongarch/loongarch-def-array.h
>   delete mode 100644 gcc/config/loongarch/loongarch-def.c
>   create mode 100644 gcc/config/loongarch/loongarch-def.cc
>   create mode 100644 gcc/testsuite/gcc.target/loongarch/div-div32.c
>   create mode 100644 gcc/testsuite/gcc.target/loongarch/div-no-div32.c
>