From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from nh504-vm9.bullet.mail.kks.yahoo.co.jp (nh504-vm9.bullet.mail.kks.yahoo.co.jp [183.79.57.95]) by sourceware.org (Postfix) with SMTP id BE4143898392 for ; Sat, 11 Jun 2022 03:32:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org BE4143898392 Received: from [183.79.100.141] by nh504.bullet.mail.kks.yahoo.co.jp with NNFMP; 11 Jun 2022 03:32:36 -0000 Received: from [183.79.101.120] by t504.bullet.mail.kks.yahoo.co.jp with NNFMP; 11 Jun 2022 03:32:35 -0000 Received: from [127.0.0.1] by omp507.mail.kks.yahoo.co.jp with NNFMP; 11 Jun 2022 03:32:35 -0000 X-Yahoo-Newman-Property: ymail-3 X-Yahoo-Newman-Id: 589791.95474.bm@omp507.mail.kks.yahoo.co.jp Received: (qmail 84915 invoked by alias); 11 Jun 2022 03:32:35 -0000 Received: from unknown (HELO ?192.168.2.3?) (175.177.45.176 with ) by smtp6004.mail.ssk.ynwp.yahoo.co.jp with SMTP; 11 Jun 2022 03:32:35 -0000 X-YMail-JAS: nCayGQwVM1ltvqwpZfgrIXPAXrgLQ1KoBOrjVdkq2Hv2NWIsN1AS_GWuHO52Tw5HxzhoQwQRh1TCf3BRLxeVrcigwh_FJP23t0uWRQhgA4h9h0K0LnejbfzS88WccWShaD7crlu6Rg-- X-Apparently-From: X-YMail-OSG: XR4T5.wVM1ms8yvAGPd86Xxr4z7SAoGnFpS9YaqlTwVhZe0 2QAdUKfBuy.NXyANNW3ewHLlSXh3_Tq_I3dEILlhA3lBvtyvskxZqncNuqRn FQfB4eo8Zw1..vR8Id29d9RXSRMxyyotz1e6L_2uWAGMn1F5y.5cCNWK8TDq hg4LOlEwpO0if2ykyhavwEZnKCpNL.Cr.hEGlGhkolTlPXLrOmAiwIclLKAo _WCdvbL4edcxMxcCUlBNipkvmHzThy4NKFWIvpBzYyW8.kn190I7jcZFu1._ loaTI.U8XpBpHfdiSm4eOwIpvq7KTP3YwpAb8JPSh2YXSbN6j.sm1aonKios rXaF5qGKGG5dnJnu62HBFafOmn1V9aUPuzkbDKgDVyPO7rat1V1BfAf03B2H uFlM1cKG8PDfyknMLZeatSaZdir0oy6MscKrpBQLjL_nbc0tPbtPggfx40Ri D44yKRiNqwa_TtmoR4z4UQytWZQpKsAJe6iNNeBYjiO0nQJwfBtn4ijli8ik YM7TTaEmbdli5gr7s0HWDO5yoGbX.8vcuDQdqQh43J5uG9Wp3YeueS313ArF Lw.t9ETz0Fwh7bkarI4NsWYBzk5WQqqZoSPvTIwOQn2fftRNucKMj7VWy09m _nKBlm2_7vPtw0RcLORp0RSW55.Jz_CeDXE6_qSjLMVqxh2A.qqRf4nN6eoi xk87qL5Z5uhY2CaIFUzsbd7NTvZz1TXjQE_XWZq9tlfMNWLG3lZoMeYTwsP_ Y4oLiDfuGShPC8xa8yIUg5kFDIwkYKWhQpD0JLq5a_PgCXZkTyhQhXohcnnu BWQW2RihEjjx1yRFBkDL4j6rIilMT3RyO4wJZoLrZKtmjFMBkWNQ2tZ1hFdz QPBdw0WP2a_HzVdpV1bt8K8M0cCLAIONmy.4zCjfdr26Y1DJXhxPUH4Qkmjw Fl4zcGCpIvlgxH.7YKw-- Message-ID: Date: Sat, 11 Jun 2022 12:31:06 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 From: Takayuki 'January June' Suwa Subject: Re: [PATCH 2/4] xtensa: Consider the Loop Option when setmemsi is expanded to small loop To: Max Filippov Cc: GCC Patches References: <842bf876-2f00-7216-b6f4-e625a13868dc@yahoo.co.jp> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-13.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, GIT_PATCH_0, NICE_REPLY_A, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 11 Jun 2022 03:32:40 -0000 On 2022/06/11 9:12, Max Filippov wrote: > Hi Suwa-san, hi! > This change results in a bunch of ICEs in tests that look like this: > > gcc/gcc/testsuite/gcc.c-torture/compile/memtst.c: In function 'main': > gcc/gcc/testsuite/gcc.c-torture/compile/memtst.c:28:1: error: > unrecognizable insn: > (insn 7 6 8 2 (set (reg:SI 45) > (plus:SI (reg:SI 44) > (const_int 262144 [0x40000]))) oh, what a my mistake... it's so RISCy! int array[65535]; void test(void) { __builtin_memset(array, 0, sizeof(array)); } .literal_position .literal .LC0, array .literal .LC2, 65535 test: l32r a3, .LC0 l32r a2, .LC2 movi.n a4, 0 loop a2, .L2_LEND .L2: s32i.n a4, a3, 0 addi.n a3, a3, 4 .L2_LEND: ret.n --- gcc/config/xtensa/xtensa.cc | 71 ++++++++++++++++++++++++++----------- 1 file changed, 50 insertions(+), 21 deletions(-) diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc index c7b54babc37..bc3330f836f 100644 --- a/gcc/config/xtensa/xtensa.cc +++ b/gcc/config/xtensa/xtensa.cc @@ -1483,7 +1483,7 @@ xtensa_expand_block_set_unrolled_loop (rtx *operands) int xtensa_expand_block_set_small_loop (rtx *operands) { - HOST_WIDE_INT bytes, value, align; + HOST_WIDE_INT bytes, value, align, count; int expand_len, funccall_len; rtx x, dst, end, reg; machine_mode unit_mode; @@ -1503,17 +1503,25 @@ xtensa_expand_block_set_small_loop (rtx *operands) /* Totally-aligned block only. */ if (bytes % align != 0) return 0; + count = bytes / align; - /* If 4-byte aligned, small loop substitution is almost optimal, thus - limited to only offset to the end address for ADDI/ADDMI instruction. */ - if (align == 4 - && ! (bytes <= 127 || (bytes <= 32512 && bytes % 256 == 0))) - return 0; + /* If the Loop Option (zero-overhead looping) is configured and active, + almost no restrictions about the length of the block. */ + if (! (TARGET_LOOPS && optimize)) + { + /* If 4-byte aligned, small loop substitution is almost optimal, + thus limited to only offset to the end address for ADDI/ADDMI + instruction. */ + if (align == 4 + && ! (bytes <= 127 || (bytes <= 32512 && bytes % 256 == 0))) + return 0; - /* If no 4-byte aligned, loop count should be treated as the constraint. */ - if (align != 4 - && bytes / align > ((optimize > 1 && !optimize_size) ? 8 : 15)) - return 0; + /* If no 4-byte aligned, loop count should be treated as the + constraint. */ + if (align != 4 + && count > ((optimize > 1 && !optimize_size) ? 8 : 15)) + return 0; + } /* Insn expansion: holding the init value. Either MOV(.N) or L32R w/litpool. */ @@ -1523,16 +1531,33 @@ xtensa_expand_block_set_small_loop (rtx *operands) expand_len = TARGET_DENSITY ? 2 : 3; else expand_len = 3 + 4; - /* Insn expansion: Either ADDI(.N) or ADDMI for the end address. */ - expand_len += bytes > 127 ? 3 - : (TARGET_DENSITY && bytes <= 15) ? 2 : 3; - - /* Insn expansion: the loop body and branch instruction. - For store, one of S8I, S16I or S32I(.N). - For advance, ADDI(.N). - For branch, BNE. */ - expand_len += (TARGET_DENSITY && align == 4 ? 2 : 3) - + (TARGET_DENSITY ? 2 : 3) + 3; + if (TARGET_LOOPS && optimize) /* zero-overhead looping */ + { + /* Insn translation: Either MOV(.N) or L32R w/litpool for the + loop count. */ + expand_len += xtensa_simm12b (count) ? xtensa_sizeof_MOVI (count) + : 3 + 4; + /* Insn translation: LOOP, the zero-overhead looping setup + instruction. */ + expand_len += 3; + /* Insn expansion: the loop body instructions. + For store, one of S8I, S16I or S32I(.N). + For advance, ADDI(.N). */ + expand_len += (TARGET_DENSITY && align == 4 ? 2 : 3) + + (TARGET_DENSITY ? 2 : 3); + } + else /* NO zero-overhead looping */ + { + /* Insn expansion: Either ADDI(.N) or ADDMI for the end address. */ + expand_len += bytes > 127 ? 3 + : (TARGET_DENSITY && bytes <= 15) ? 2 : 3; + /* Insn expansion: the loop body and branch instruction. + For store, one of S8I, S16I or S32I(.N). + For advance, ADDI(.N). + For branch, BNE. */ + expand_len += (TARGET_DENSITY && align == 4 ? 2 : 3) + + (TARGET_DENSITY ? 2 : 3) + 3; + } /* Function call: preparing two arguments. */ funccall_len = xtensa_sizeof_MOVI (value); @@ -1555,7 +1580,11 @@ xtensa_expand_block_set_small_loop (rtx *operands) dst = gen_reg_rtx (SImode); emit_move_insn (dst, x); end = gen_reg_rtx (SImode); - emit_insn (gen_addsi3 (end, dst, operands[1] /* the length */)); + if (TARGET_LOOPS && optimize) + x = force_reg (SImode, operands[1] /* the length */); + else + x = operands[1]; + emit_insn (gen_addsi3 (end, dst, x)); switch (align) { case 1: -- 2.20.1