Re: [PATCH v3] RISC-V: Fix regression of -fzero-call-used-regs=all

[Jeff Law <jeffreyalaw@gmail.com>]

On 4/7/23 06:32, yanzhang.wang--- via Gcc-patches wrote:
> From: Yanzhang Wang <yanzhang.wang@intel.com>
> 
> This patch registers a riscv specific function to
> TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will
> clean gpr and vector relevant registers.
> 
> 	PR 109104
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/riscv-protos.h (emit_hard_vlmax_vsetvl):
> 	* config/riscv/riscv-v.cc (emit_hard_vlmax_vsetvl):
> 	(emit_vlmax_vsetvl):
> 	* config/riscv/riscv.cc (vector_zero_call_used_regs):
> 	(riscv_zero_call_used_regs):
> 	(TARGET_ZERO_CALL_USED_REGS):
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/zero-scratch-regs-1.c: New test.
> 	* gcc.target/riscv/zero-scratch-regs-2.c: New test.
> 	* gcc.target/riscv/zero-scratch-regs-3.c: New test.
Presumably the difficulty here is we need to find a suitable hard 
register so that we can emit the vsetvl.


> 
> Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
> Co-authored-by: Pan Li <pan2.li@intel.com>
> Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
> ---
>   gcc/config/riscv/riscv-protos.h               |  1 +
>   gcc/config/riscv/riscv-v.cc                   | 15 +++-
>   gcc/config/riscv/riscv.cc                     | 71 +++++++++++++++++++
>   .../gcc.target/riscv/zero-scratch-regs-1.c    |  9 +++
>   .../gcc.target/riscv/zero-scratch-regs-2.c    | 24 +++++++
>   .../gcc.target/riscv/zero-scratch-regs-3.c    | 57 +++++++++++++++
>   6 files changed, 174 insertions(+), 3 deletions(-)
>   create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
>   create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
>   create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c
> 
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 2e91d019f6c..13dd6639c9f 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -118,6 +118,17 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,
>   	  && IN_RANGE (INTVAL (elt), minval, maxval));
>   }
>   
> +/* Emit a vlmax vsetvl instruction with side effect, this should be only used
> +   when optimization is tune off or emit after vsetvl insertion pass.  */
Minor grammar errors.  I'd probably write it as:

/* Emit a vlvax vsetvl instruction.  This should only be used
    when optimization is disabled or after the vsetvl insertion pass.  */


Do you need to save/restore the vector configuration before and after 
clearing the vector registers?    If so, that seems to be missing.  If 
not, it seems like a comment explaining why would be useful.




Jeff