From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by sourceware.org (Postfix) with ESMTPS id 5AFD83858401 for ; Mon, 28 Nov 2022 23:54:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5AFD83858401 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pj1-x1029.google.com with SMTP id hd14-20020a17090b458e00b0021909875bccso148428pjb.1 for ; Mon, 28 Nov 2022 15:54:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=q87vYuE6KR5p2QzCJ2wFAd2TJvYTSibiPl/roOhgHjU=; b=VDbGdAqtB6dJjrbVkXjqplnGS+hW64kQ0sSnrkjPG9znlkZZz0sogN8USjm2Rjucad nmFS0FcUKC3bGhsjajZMM2/36q3XkA7L/7AmCU9XRriqzNcRRZtTNbQMWVpfUzYkRY33 B14c4Z/HNNc0vVX49EhRmvYlFTXlWnSl/tGdVbjyNDMuaFkI9Nn/2qzTIFtO6YNq5YIo fA7rsWyhj8Lf1OBOnJmf4qBFxBU8HFGckHqW0Qy7HGcZ/7MCM7CsgRVuLVxBjVHBji3H oPvyWFlz0eUpQ+i7l/YAUU6qyCyAKbYRMdtv32A5mCajTc8whM2UKLRIsql5T7cSjUwD WuVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=q87vYuE6KR5p2QzCJ2wFAd2TJvYTSibiPl/roOhgHjU=; b=Vo0hB5ShdDT9Sn3UWLR5U1cHd/a8q57SoNPOPCBUZTLB8su8CsD+SIwAeSsE+0+u4D 0zPDFMPC4GN6ziMhf+OxTJ+7tAf8sV3y6+rke0mU5cvdbry0CzSs3FWUipEaJzFQd8Wv PPUbsPlK1NeLJX58LYp1zc2cOUh0Pu0aUk1atlPmlBrHycKnD41/9nq1OnBDkk+xV2iQ y81au13c3R5UIwy9YG59TEYGtyGxY+GmsGm8yhKaa1grXMs104y0SWMVieIDHNElN1/w wAdjsV1KXMqvMVWzjSaMV7eANCXXUpJovLU1ZG4/eyruemR5BF++Rqxa8CIQgTCKaLLF AKUA== X-Gm-Message-State: ANoB5pnD2sZT8rZ5smvhIXxOgm5vWNxsQq0LugKzc0WXu7P72jknB7YU foELgbv4/0pNuTHVQ0ReJfg= X-Google-Smtp-Source: AA0mqf7k6E2xVrfNnJZwmvyHtq9ofTtcs7CQkEd312EkOATi2m7zdHMLd+Fd8+fzmcDRsJ5UcEB4uA== X-Received: by 2002:a17:90a:4594:b0:218:f745:76fe with SMTP id v20-20020a17090a459400b00218f74576femr25415483pjg.245.1669679652056; Mon, 28 Nov 2022 15:54:12 -0800 (PST) Received: from ?IPV6:2601:681:8600:13d0::f0a? ([2601:681:8600:13d0::f0a]) by smtp.gmail.com with ESMTPSA id m127-20020a625885000000b0056bc5ad4862sm8567859pfb.28.2022.11.28.15.54.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Nov 2022 15:54:11 -0800 (PST) Message-ID: Date: Mon, 28 Nov 2022 16:54:10 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [PATCH] RISC-V: Add attributes for VSETVL PASS Content-Language: en-US To: =?UTF-8?B?6ZKf5bGF5ZOy?= , gcc-patches Cc: "kito.cheng" , palmer References: <20221128141406.242953-1-juzhe.zhong@rivai.ai> <7BF53C765A4D8817+202211290652169080217@rivai.ai> From: Jeff Law In-Reply-To: <7BF53C765A4D8817+202211290652169080217@rivai.ai> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 11/28/22 15:52, 钟居哲 wrote: > >> I'm tempted to push this into the next stage1 given its arrival after >>>stage1 close, but if the wider RISC-V maintainers want to see it move >>>forward, I don't object strongly. > > Ok, let's save these patches and merge them when GCC14 stage1 is open. > Would you mind telling me when will stage 1 be open? Typically it's April. As was noted elsewhere, feel free to keep submitting patches in this space and you can certainly create a branch where y'all can put patches to make it easier to collaborate and ultimately merge with the trunk once stage1 is open again. > > >> I'm curious about the model you're using.  Is it going to be something >>>similar to mode switching?  That's the first mental model that comes to >>>mind.  Essentially we determine the VL needed for every chunk of code, >>>then we do an LCM like algorithm to find the optimal placement points >>>for VL sets to minimize the number of VL sets across all the paths >>>through the CFG.  Never in a million years would I have expected we'd be >>>considering reusing that code. > > Yes, I implemented VSETVL PASS with LCM algorithm and RTL_SSA framework. Yea, layering on top of RTL-SSA is probably better than the existing mode-switching which is LCM without SSA. > Actually, me && kito have spent a month on VSETVL PASS and we have > made a progress. We have tested it with a lot of testcases, turns out > our implementation > of VSETVL PASS in GCC has much better codegen than the VSETVL implemented > in LLVM side in many different situations because of LCM. I am working > on cleaning up the codes > and hopefully you will see it soon in the next patch. Good to hear. I argued pretty loudly in the late 90s that LCM was the right framework for this problem. We didn't have rtl-ssa, but we did have a pure RTL LCM module that Joern and Andrew were able to re-use to implement sh's mode switching. I just never thought we'd see another processor where it'd be useful. Jeff