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[24.4.73.83]) by smtp.gmail.com with ESMTPSA id z26-20020a62d11a000000b0053e5daf1a25sm9432621pfg.45.2022.10.11.12.06.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Oct 2022 12:06:28 -0700 (PDT) Message-ID: Date: Tue, 11 Oct 2022 12:06:27 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v2 00/10] [RISC-V] Atomics improvements [PR100265/PR100266] Content-Language: en-US To: Christoph Muellner , gcc-patches@gcc.gnu.org Cc: Kito Cheng , gnu-toolchain References: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> From: Vineet Gupta In-Reply-To: <20210505193651.2075405-1-cmuellner@gcc.gnu.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,KAM_SHORT,NICE_REPLY_A,RCVD_IN_BARRACUDACENTRAL,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Christoph, Kito, On 5/5/21 12:36, Christoph Muellner via Gcc-patches wrote: > This series provides a cleanup of the current atomics implementation > of RISC-V: > > * PR100265: Use proper fences for atomic load/store > * PR100266: Provide programmatic implementation of CAS > > As both are very related, I merged the patches into one series. > > The first patch could be squashed into the following patches, > but I found it easier to understand the chances with it in place. > > The series has been tested as follows: > * Building and testing a multilib RV32/64 toolchain > (bootstrapped with riscv-gnu-toolchain repo) > * Manual review of generated sequences for GCC's atomic builtins API > > The programmatic re-implementation of CAS benefits from a REE improvement > (see PR100264): > https://gcc.gnu.org/pipermail/gcc-patches/2021-April/568680.html > If this patch is not in place, then an additional extension instruction > is emitted after the SC.W (in case of RV64 and CAS for uint32_t). > > Further, the new CAS code requires cbranch INSN helpers to be present: > https://gcc.gnu.org/pipermail/gcc-patches/2021-May/569689.html I was wondering is this patchset is blocked on some technical grounds. Thx, -Vineet > Changes for v2: > * Guard LL/SC sequence by compiler barriers ("blockage") > (suggested by Andrew Waterman) > * Changed commit message for AMOSWAP->STORE change > (suggested by Andrew Waterman) > * Extracted cbranch4 patch from patchset (suggested by Kito Cheng) > * Introduce predicate riscv_sync_memory_operand (suggested by Jim Wilson) > * Fix small code style issue > > Christoph Muellner (10): > RISC-V: Simplify memory model code [PR 100265] > RISC-V: Emit proper memory ordering suffixes for AMOs [PR 100265] > RISC-V: Eliminate %F specifier from riscv_print_operand() [PR 100265] > RISC-V: Use STORE instead of AMOSWAP for atomic stores [PR 100265] > RISC-V: Emit fences according to chosen memory model [PR 100265] > RISC-V: Implement atomic_{load,store} [PR 100265] > RISC-V: Model INSNs for LR and SC [PR 100266] > RISC-V: Add s.ext-consuming INSNs for LR and SC [PR 100266] > RISC-V: Provide programmatic implementation of CAS [PR 100266] > RISC-V: Introduce predicate "riscv_sync_memory_operand" [PR 100266] > > gcc/config/riscv/riscv-protos.h | 1 + > gcc/config/riscv/riscv.c | 136 +++++++++++++------- > gcc/config/riscv/sync.md | 216 +++++++++++++++++++++----------- > 3 files changed, 235 insertions(+), 118 deletions(-) >