From: Patrick O'Neill <patrick@rivosinc.com>
To: gcc-patches@gcc.gnu.org
Cc: gnu-toolchain@rivosinc.com, dlustig@nvidia.com,
kito.cheng@sifive.com, palmer@rivosinc.com, vineetg@rivosinc.com,
andrew@sifive.com
Subject: Re: [RFC 0/7] RISCV: Implement ISA Manual Table A.6 Mappings
Date: Mon, 9 May 2022 17:52:58 -0700 [thread overview]
Message-ID: <f356ac0e-677f-17fd-1ccc-7fb4b4b41891@rivosinc.com> (raw)
In-Reply-To: <20220407183351.295188-1-patrick@rivosinc.com>
The litmus test in this RFC is flawed since it does not assert that the
LR/SC pair succeeds. The condition in the RFC is permitted iff the LR/SC
pair fails. After correcting this flaw [1][2], the litmus test condition
is correctly forbidden.
This correction does not mean that the A.6 mapping is guaranteed to be
fully compatible with the current GCC/LLVM mapping. This just means that
this particular case does not appear to be an issue.
Thanks,
Patrick
[1] Corrected herd7 litmus test:
RISCV W-RMW
{
0:x7=A; 0:x8=B; 0:x1=1;
1:x7=A; 1:x8=B; 1:x1=1;
}
P0 | P1 ;
fence rw,w | fence rw,rw ;
sw x1,0(x8) | sw x1,0(x7) ;
lr.w.aq x3,0(x7) | fence rw,rw ;
sc.w.rl x2,x1,0(x7) | lw x2,0(x8) ;
~exists (0:x2=0 /\ 0:x3=0 /\ 1:x2=0)
[2] Corrected herd7 litmus test (with retry-loop):
RISCV W-RMW
{
0:x7=A; 0:x8=B; 0:x1=1;
1:x7=A; 1:x8=B; 1:x1=1;
}
P0 | P1 ;
fence rw,w | sw x1,0(x7) ;
sw x1,0(x8) | fence rw,rw ;
LC00: | lw x2,0(x8) ;
lr.w.aq x3,0(x7) | ;
sc.w.rl x2,x1,0(x7) | ;
bne x2,x0,LC00 | ;
~exists (0:x2=0 /\ 0:x3=0 /\ 1:x2=0)
prev parent reply other threads:[~2022-05-10 0:53 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-07 18:33 Patrick O'Neill
2022-04-07 18:33 ` [RFC 1/7] RISCV: Enforce Libatomic LR/SC SEQ_CST Patrick O'Neill
2022-04-07 18:33 ` [RFC 2/7] RISCV: Enforce Atomic Compare Exchange SEQ_CST Patrick O'Neill
2022-04-07 18:33 ` [RFC 3/7] RISCV: Add AMO release bits Patrick O'Neill
2022-04-07 18:33 ` [RFC 4/7] RISCV: Optimize AMO Ops Patrick O'Neill
2022-04-07 18:33 ` [RFC 5/7] RISCV: Optimize LR/SC Pairs Patrick O'Neill
2022-04-07 18:33 ` [RFC 6/7] RISCV: Optimize Atomic Stores Patrick O'Neill
2022-04-07 18:33 ` [RFC 7/7] RISCV: Relax mem_thread_fence Patrick O'Neill
2022-05-10 0:52 ` Patrick O'Neill [this message]
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