* [PATCH v2] LoongArch: Optimize single-used address with -mexplicit-relocs=auto for fld/fst
@ 2023-11-11 10:58 Xi Ruoyao
2023-11-13 3:27 ` chenglulu
0 siblings, 1 reply; 2+ messages in thread
From: Xi Ruoyao @ 2023-11-11 10:58 UTC (permalink / raw)
To: gcc-patches; +Cc: chenglulu, i, xuchenghua, Xi Ruoyao
fld and fst have same address mode as ld.w and st.w, so the same
optimization as r14-4851 should be applied for them too.
gcc/ChangeLog:
* config/loongarch/loongarch.md (LD_AT_LEAST_32_BIT): New mode
iterator.
(ST_ANY): New mode iterator.
(define_peephole2): Use LD_AT_LEAST_32_BIT instead of GPR and
ST_ANY instead of QHWD for applicable patterns.
---
v1: https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635278.html
Changes from v1: take the advantage of r14-5329 "Allow md iterators to
include other iterators" to simplify LD_AT_LEAST_32_BIT and ST_ANY.
Ok for trunk?
gcc/config/loongarch/loongarch.md | 38 +++++++++++++++++++------------
1 file changed, 24 insertions(+), 14 deletions(-)
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index 4dd716e1941..22814a3679c 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -400,6 +400,14 @@ (define_mode_iterator SPLITF
(DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
(TF "TARGET_64BIT && TARGET_DOUBLE_FLOAT")])
+;; A mode for anything with 32 bits or more, and able to be loaded with
+;; the same addressing mode as ld.w.
+(define_mode_iterator LD_AT_LEAST_32_BIT [GPR ANYF])
+
+;; A mode for anything able to be stored with the same addressing mode as
+;; st.w.
+(define_mode_iterator ST_ANY [QHWD ANYF])
+
;; In GPR templates, a string like "mul.<d>" will expand to "mul.w" in the
;; 32-bit version and "mul.d" in the 64-bit version.
(define_mode_attr d [(SI "w") (DI "d")])
@@ -3785,13 +3793,14 @@ (define_insn "loongarch_crcc_w_<size>_w"
(define_peephole2
[(set (match_operand:P 0 "register_operand")
(match_operand:P 1 "symbolic_pcrel_operand"))
- (set (match_operand:GPR 2 "register_operand")
- (mem:GPR (match_dup 0)))]
+ (set (match_operand:LD_AT_LEAST_32_BIT 2 "register_operand")
+ (mem:LD_AT_LEAST_32_BIT (match_dup 0)))]
"la_opt_explicit_relocs == EXPLICIT_RELOCS_AUTO \
&& (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \
&& (peep2_reg_dead_p (2, operands[0]) \
|| REGNO (operands[0]) == REGNO (operands[2]))"
- [(set (match_dup 2) (mem:GPR (lo_sum:P (match_dup 0) (match_dup 1))))]
+ [(set (match_dup 2)
+ (mem:LD_AT_LEAST_32_BIT (lo_sum:P (match_dup 0) (match_dup 1))))]
{
emit_insn (gen_pcalau12i_gr<P:mode> (operands[0], operands[1]));
})
@@ -3799,14 +3808,15 @@ (define_peephole2
(define_peephole2
[(set (match_operand:P 0 "register_operand")
(match_operand:P 1 "symbolic_pcrel_operand"))
- (set (match_operand:GPR 2 "register_operand")
- (mem:GPR (plus (match_dup 0)
- (match_operand 3 "const_int_operand"))))]
+ (set (match_operand:LD_AT_LEAST_32_BIT 2 "register_operand")
+ (mem:LD_AT_LEAST_32_BIT (plus (match_dup 0)
+ (match_operand 3 "const_int_operand"))))]
"la_opt_explicit_relocs == EXPLICIT_RELOCS_AUTO \
&& (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \
&& (peep2_reg_dead_p (2, operands[0]) \
|| REGNO (operands[0]) == REGNO (operands[2]))"
- [(set (match_dup 2) (mem:GPR (lo_sum:P (match_dup 0) (match_dup 1))))]
+ [(set (match_dup 2)
+ (mem:LD_AT_LEAST_32_BIT (lo_sum:P (match_dup 0) (match_dup 1))))]
{
operands[1] = plus_constant (Pmode, operands[1], INTVAL (operands[3]));
emit_insn (gen_pcalau12i_gr<P:mode> (operands[0], operands[1]));
@@ -3850,13 +3860,13 @@ (define_peephole2
(define_peephole2
[(set (match_operand:P 0 "register_operand")
(match_operand:P 1 "symbolic_pcrel_operand"))
- (set (mem:QHWD (match_dup 0))
- (match_operand:QHWD 2 "register_operand"))]
+ (set (mem:ST_ANY (match_dup 0))
+ (match_operand:ST_ANY 2 "register_operand"))]
"la_opt_explicit_relocs == EXPLICIT_RELOCS_AUTO \
&& (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \
&& (peep2_reg_dead_p (2, operands[0])) \
&& REGNO (operands[0]) != REGNO (operands[2])"
- [(set (mem:QHWD (lo_sum:P (match_dup 0) (match_dup 1))) (match_dup 2))]
+ [(set (mem:ST_ANY (lo_sum:P (match_dup 0) (match_dup 1))) (match_dup 2))]
{
emit_insn (gen_pcalau12i_gr<P:mode> (operands[0], operands[1]));
})
@@ -3864,14 +3874,14 @@ (define_peephole2
(define_peephole2
[(set (match_operand:P 0 "register_operand")
(match_operand:P 1 "symbolic_pcrel_operand"))
- (set (mem:QHWD (plus (match_dup 0)
- (match_operand 3 "const_int_operand")))
- (match_operand:QHWD 2 "register_operand"))]
+ (set (mem:ST_ANY (plus (match_dup 0)
+ (match_operand 3 "const_int_operand")))
+ (match_operand:ST_ANY 2 "register_operand"))]
"la_opt_explicit_relocs == EXPLICIT_RELOCS_AUTO \
&& (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \
&& (peep2_reg_dead_p (2, operands[0])) \
&& REGNO (operands[0]) != REGNO (operands[2])"
- [(set (mem:QHWD (lo_sum:P (match_dup 0) (match_dup 1))) (match_dup 2))]
+ [(set (mem:ST_ANY (lo_sum:P (match_dup 0) (match_dup 1))) (match_dup 2))]
{
operands[1] = plus_constant (Pmode, operands[1], INTVAL (operands[3]));
emit_insn (gen_pcalau12i_gr<P:mode> (operands[0], operands[1]));
--
2.42.1
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH v2] LoongArch: Optimize single-used address with -mexplicit-relocs=auto for fld/fst
2023-11-11 10:58 [PATCH v2] LoongArch: Optimize single-used address with -mexplicit-relocs=auto for fld/fst Xi Ruoyao
@ 2023-11-13 3:27 ` chenglulu
0 siblings, 0 replies; 2+ messages in thread
From: chenglulu @ 2023-11-13 3:27 UTC (permalink / raw)
To: Xi Ruoyao, gcc-patches; +Cc: i, xuchenghua
在 2023/11/11 下午6:58, Xi Ruoyao 写道:
> fld and fst have same address mode as ld.w and st.w, so the same
> optimization as r14-4851 should be applied for them too.
>
> gcc/ChangeLog:
>
> * config/loongarch/loongarch.md (LD_AT_LEAST_32_BIT): New mode
> iterator.
> (ST_ANY): New mode iterator.
> (define_peephole2): Use LD_AT_LEAST_32_BIT instead of GPR and
> ST_ANY instead of QHWD for applicable patterns.
> ---
>
> v1: https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635278.html
>
> Changes from v1: take the advantage of r14-5329 "Allow md iterators to
> include other iterators" to simplify LD_AT_LEAST_32_BIT and ST_ANY.
>
> Ok for trunk?
LGTM!
Thanks!
>
> gcc/config/loongarch/loongarch.md | 38 +++++++++++++++++++------------
> 1 file changed, 24 insertions(+), 14 deletions(-)
>
> diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
> index 4dd716e1941..22814a3679c 100644
> --- a/gcc/config/loongarch/loongarch.md
> +++ b/gcc/config/loongarch/loongarch.md
> @@ -400,6 +400,14 @@ (define_mode_iterator SPLITF
> (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
> (TF "TARGET_64BIT && TARGET_DOUBLE_FLOAT")])
>
> +;; A mode for anything with 32 bits or more, and able to be loaded with
> +;; the same addressing mode as ld.w.
> +(define_mode_iterator LD_AT_LEAST_32_BIT [GPR ANYF])
> +
> +;; A mode for anything able to be stored with the same addressing mode as
> +;; st.w.
> +(define_mode_iterator ST_ANY [QHWD ANYF])
> +
> ;; In GPR templates, a string like "mul.<d>" will expand to "mul.w" in the
> ;; 32-bit version and "mul.d" in the 64-bit version.
> (define_mode_attr d [(SI "w") (DI "d")])
> @@ -3785,13 +3793,14 @@ (define_insn "loongarch_crcc_w_<size>_w"
> (define_peephole2
> [(set (match_operand:P 0 "register_operand")
> (match_operand:P 1 "symbolic_pcrel_operand"))
> - (set (match_operand:GPR 2 "register_operand")
> - (mem:GPR (match_dup 0)))]
> + (set (match_operand:LD_AT_LEAST_32_BIT 2 "register_operand")
> + (mem:LD_AT_LEAST_32_BIT (match_dup 0)))]
> "la_opt_explicit_relocs == EXPLICIT_RELOCS_AUTO \
> && (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \
> && (peep2_reg_dead_p (2, operands[0]) \
> || REGNO (operands[0]) == REGNO (operands[2]))"
> - [(set (match_dup 2) (mem:GPR (lo_sum:P (match_dup 0) (match_dup 1))))]
> + [(set (match_dup 2)
> + (mem:LD_AT_LEAST_32_BIT (lo_sum:P (match_dup 0) (match_dup 1))))]
> {
> emit_insn (gen_pcalau12i_gr<P:mode> (operands[0], operands[1]));
> })
> @@ -3799,14 +3808,15 @@ (define_peephole2
> (define_peephole2
> [(set (match_operand:P 0 "register_operand")
> (match_operand:P 1 "symbolic_pcrel_operand"))
> - (set (match_operand:GPR 2 "register_operand")
> - (mem:GPR (plus (match_dup 0)
> - (match_operand 3 "const_int_operand"))))]
> + (set (match_operand:LD_AT_LEAST_32_BIT 2 "register_operand")
> + (mem:LD_AT_LEAST_32_BIT (plus (match_dup 0)
> + (match_operand 3 "const_int_operand"))))]
> "la_opt_explicit_relocs == EXPLICIT_RELOCS_AUTO \
> && (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \
> && (peep2_reg_dead_p (2, operands[0]) \
> || REGNO (operands[0]) == REGNO (operands[2]))"
> - [(set (match_dup 2) (mem:GPR (lo_sum:P (match_dup 0) (match_dup 1))))]
> + [(set (match_dup 2)
> + (mem:LD_AT_LEAST_32_BIT (lo_sum:P (match_dup 0) (match_dup 1))))]
> {
> operands[1] = plus_constant (Pmode, operands[1], INTVAL (operands[3]));
> emit_insn (gen_pcalau12i_gr<P:mode> (operands[0], operands[1]));
> @@ -3850,13 +3860,13 @@ (define_peephole2
> (define_peephole2
> [(set (match_operand:P 0 "register_operand")
> (match_operand:P 1 "symbolic_pcrel_operand"))
> - (set (mem:QHWD (match_dup 0))
> - (match_operand:QHWD 2 "register_operand"))]
> + (set (mem:ST_ANY (match_dup 0))
> + (match_operand:ST_ANY 2 "register_operand"))]
> "la_opt_explicit_relocs == EXPLICIT_RELOCS_AUTO \
> && (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \
> && (peep2_reg_dead_p (2, operands[0])) \
> && REGNO (operands[0]) != REGNO (operands[2])"
> - [(set (mem:QHWD (lo_sum:P (match_dup 0) (match_dup 1))) (match_dup 2))]
> + [(set (mem:ST_ANY (lo_sum:P (match_dup 0) (match_dup 1))) (match_dup 2))]
> {
> emit_insn (gen_pcalau12i_gr<P:mode> (operands[0], operands[1]));
> })
> @@ -3864,14 +3874,14 @@ (define_peephole2
> (define_peephole2
> [(set (match_operand:P 0 "register_operand")
> (match_operand:P 1 "symbolic_pcrel_operand"))
> - (set (mem:QHWD (plus (match_dup 0)
> - (match_operand 3 "const_int_operand")))
> - (match_operand:QHWD 2 "register_operand"))]
> + (set (mem:ST_ANY (plus (match_dup 0)
> + (match_operand 3 "const_int_operand")))
> + (match_operand:ST_ANY 2 "register_operand"))]
> "la_opt_explicit_relocs == EXPLICIT_RELOCS_AUTO \
> && (TARGET_CMODEL_NORMAL || TARGET_CMODEL_MEDIUM) \
> && (peep2_reg_dead_p (2, operands[0])) \
> && REGNO (operands[0]) != REGNO (operands[2])"
> - [(set (mem:QHWD (lo_sum:P (match_dup 0) (match_dup 1))) (match_dup 2))]
> + [(set (mem:ST_ANY (lo_sum:P (match_dup 0) (match_dup 1))) (match_dup 2))]
> {
> operands[1] = plus_constant (Pmode, operands[1], INTVAL (operands[3]));
> emit_insn (gen_pcalau12i_gr<P:mode> (operands[0], operands[1]));
^ permalink raw reply [flat|nested] 2+ messages in thread
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2023-11-13 3:27 ` chenglulu
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