From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 4EB263858C78 for ; Thu, 27 Jan 2022 11:51:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 4EB263858C78 Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 20RBaRIS006614; Thu, 27 Jan 2022 11:51:01 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 3dupsuny8t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Jan 2022 11:51:01 +0000 Received: from m0098409.ppops.net (m0098409.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.43/8.16.0.43) with SMTP id 20RBcrSe022333; Thu, 27 Jan 2022 11:51:00 GMT Received: from ppma02fra.de.ibm.com (47.49.7a9f.ip4.static.sl-reverse.com [159.122.73.71]) by mx0a-001b2d01.pphosted.com with ESMTP id 3dupsuny81-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Jan 2022 11:51:00 +0000 Received: from pps.filterd (ppma02fra.de.ibm.com [127.0.0.1]) by ppma02fra.de.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 20RBSB0Q013346; Thu, 27 Jan 2022 11:50:58 GMT Received: from b06cxnps4076.portsmouth.uk.ibm.com (d06relay13.portsmouth.uk.ibm.com [9.149.109.198]) by ppma02fra.de.ibm.com with ESMTP id 3dr9j9wcu1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Jan 2022 11:50:58 +0000 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 20RBosP945875684 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 27 Jan 2022 11:50:55 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DE9A24204C; Thu, 27 Jan 2022 11:50:54 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 60DD842049; Thu, 27 Jan 2022 11:50:51 +0000 (GMT) Received: from KewenLins-MacBook-Pro.local (unknown [9.200.32.129]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 27 Jan 2022 11:50:51 +0000 (GMT) Subject: Re: [PATCH] rs6000: Move the hunk affecting VSX/ALTIVEC ahead [PR103627] To: Segher Boessenkool Cc: GCC Patches , David Edelsohn , Bill Schmidt , Michael Meissner References: <20220126224208.GZ614@gate.crashing.org> From: "Kewen.Lin" Message-ID: Date: Thu, 27 Jan 2022 19:50:49 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 In-Reply-To: <20220126224208.GZ614@gate.crashing.org> Content-Type: multipart/mixed; boundary="------------B21898B34293B7BC3E28CDEF" Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-GUID: fqiCFAQ_rZRHw3CFPjM3vt72YmxMheh3 X-Proofpoint-ORIG-GUID: Ce73m-Q0fMG3lYcbJQt9cO0TVz6LWCvD X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-27_03,2022-01-27_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 spamscore=0 bulkscore=0 adultscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 suspectscore=0 malwarescore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201270070 X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, MIME_CHARSET_FARAWAY, NICE_REPLY_A, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 27 Jan 2022 11:51:04 -0000 This is a multi-part message in MIME format. --------------B21898B34293B7BC3E28CDEF Content-Type: text/plain; charset=gbk Content-Transfer-Encoding: 8bit Hi Segher, on 2022/1/27 ÉÏÎç6:42, Segher Boessenkool wrote: > Hi! > > On Thu, Dec 23, 2021 at 10:12:19AM +0800, Kewen.Lin wrote: >> PR target/103627 >> * config/rs6000/rs6000.c (rs6000_option_override_internal): Move the >> hunk affecting VSX and ALTIVEC to the appropriate place. >> >> gcc/testsuite/ChangeLog: >> >> PR target/103627 >> * gcc.target/powerpc/pr103627-3.c: New test. > > >> --- a/gcc/config/rs6000/rs6000.c >> +++ b/gcc/config/rs6000/rs6000.c >> @@ -3955,6 +3955,15 @@ rs6000_option_override_internal (bool global_init_p) >> else if (TARGET_ALTIVEC) >> rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks); >> >> + /* Disable VSX and Altivec silently if the user switched cpus to power7 in a >> + target attribute or pragma which automatically enables both options, >> + unless the altivec ABI was set. This is set by default for 64-bit, but >> + not for 32-bit. Don't move this before the above code using ignore_masks, >> + since it can reset the cleared VSX/ALTIVEC flag again. */ >> + if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi) >> + rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC) >> + & ~rs6000_isa_flags_explicit); > > Could you at the same time get rid of the != NULL please? > if (bla != NULL) > is sillier than > if (bla != 0) > which is about the same as > if (!!bla) > but that is certainly better than > if (bla != 0 != 0) > although I am not sure about the more stylish > if (bla != 0 != 0 != 0 != 0 != 0) > but what is wrong with > if (bla) > ? :-) > >> +/* There are no error messages for either LE or BE 64bit. */ >> +/* { dg-require-effective-target be }*/ > > (space before */) > >> +/* { dg-require-effective-target ilp32 } */ >> +/* We don't have one powerpc.*_ok for Power6, use altivec_ok conservatively. */ >> +/* { dg-require-effective-target powerpc_altivec_ok } */ >> +/* { dg-options "-mdejagnu-cpu=power6" } */ > > It is okay always, no _ok at all please. > > Okay for trunk with those things (but do test of course). Thanks! > > Thanks for the review comments! I've addressed them in the attached patch. Besides, I updated the case a bit by adding -mno-avoid-indexed-addresses, otherwise the associated case would have one unexpected warning which is supposed to be fixed by [1]. But even with this adjustment, this patch still relies on [2], otherwise the associated case will get ICE instead. btw, it can survives in all the testings as before together with [2]. So I'll hold this to commit until [2] gets landed. [1] https://gcc.gnu.org/pipermail/gcc-patches/2021-December/587449.html [2] https://gcc.gnu.org/pipermail/gcc-patches/2022-January/589325.html BR, Kewen --------------B21898B34293B7BC3E28CDEF Content-Type: text/plain; charset=UTF-8; x-mac-type="0"; x-mac-creator="0"; name="pr103627-2.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="pr103627-2.patch" >From 90565d869395df08a65d521ddad8684a99e844a5 Mon Sep 17 00:00:00 2001 From: Kewen Lin Date: Thu, 27 Jan 2022 00:25:29 -0600 Subject: [PATCH 3/3] rs6000: Move the hunk affecting VSX/ALTIVEC ahead [PR103627] The modified hunk can update VSX and ALTIVEC flag, we have some codes to check/warn for some flags related to VSX and ALTIVEC sitting where the hunk is proprosed to be moved to. Without this adjustment, the VSX and ALTIVEC update is too late, it can cause the incompatibility and result in unexpected behaviors, the associated test case is one typical case. Since we already have the code which sets TARGET_FLOAT128_TYPE and lays after the moved place, and OPTION_MASK_FLOAT128_KEYWORD will rely on TARGET_FLOAT128_TYPE, so it just simply remove them. gcc/ChangeLog: PR target/103627 * config/rs6000/rs6000.cc (rs6000_option_override_internal): Move the hunk affecting VSX and ALTIVEC to appropriate place. gcc/testsuite/ChangeLog: PR target/103627 * gcc.target/powerpc/pr103627-3.c: New test. --- gcc/config/rs6000/rs6000.cc | 21 ++++++++----------- gcc/testsuite/gcc.target/powerpc/pr103627-3.c | 20 ++++++++++++++++++ 2 files changed, 29 insertions(+), 12 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr103627-3.c diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 634937e052f..f90fd8955cd 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3943,6 +3943,15 @@ rs6000_option_override_internal (bool global_init_p) else if (TARGET_ALTIVEC) rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks); + /* Disable VSX and Altivec silently if the user switched cpus to power7 in a + target attribute or pragma which automatically enables both options, + unless the altivec ABI was set. This is set by default for 64-bit, but + not for 32-bit. Don't move this before the above code using ignore_masks, + since it can reset the cleared VSX/ALTIVEC flag again. */ + if (main_target_opt && !main_target_opt->x_rs6000_altivec_abi) + rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC) + & ~rs6000_isa_flags_explicit); + if (TARGET_CRYPTO && !TARGET_ALTIVEC) { if (rs6000_isa_flags_explicit & OPTION_MASK_CRYPTO) @@ -4359,18 +4368,6 @@ rs6000_option_override_internal (bool global_init_p) } } - /* Disable VSX and Altivec silently if the user switched cpus to power7 in a - target attribute or pragma which automatically enables both options, - unless the altivec ABI was set. This is set by default for 64-bit, but - not for 32-bit. */ - if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi) - { - TARGET_FLOAT128_TYPE = 0; - rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC - | OPTION_MASK_FLOAT128_KEYWORD) - & ~rs6000_isa_flags_explicit); - } - /* Enable Altivec ABI for AIX -maltivec. */ if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX) diff --git a/gcc/testsuite/gcc.target/powerpc/pr103627-3.c b/gcc/testsuite/gcc.target/powerpc/pr103627-3.c new file mode 100644 index 00000000000..5a4d5ba5701 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr103627-3.c @@ -0,0 +1,20 @@ +/* There are no error messages for either LE or BE 64bit. */ +/* { dg-require-effective-target be } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-mdejagnu-cpu=power6" } */ + +/* Verify compiler emits error message instead of ICE. */ + +/* Option -mno-avoid-indexed-addresses is to disable the unexpected + warning on indexed addressing which can affect dg checks. */ +#pragma GCC target "cpu=power10,no-avoid-indexed-addresses" +int +main () +{ + float *b; + __vector_quad c; + __builtin_mma_disassemble_acc (b, &c); + /* { dg-error "'__builtin_mma_disassemble_acc' requires the '-mmma' option" "" { target *-*-* } .-1 } */ + return 0; +} + -- 2.27.0 --------------B21898B34293B7BC3E28CDEF--