From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by sourceware.org (Postfix) with ESMTPS id CE0933886A17 for ; Sat, 17 Dec 2022 01:48:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CE0933886A17 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pj1-x102c.google.com with SMTP id gt4so4120634pjb.1 for ; Fri, 16 Dec 2022 17:48:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=NQUFXWA6E8FIY5FfhI+SZs0H22qjLHwcDKCzPJiSIWg=; b=QfOMeyneC92riPPlvACPqQbXFamSXEaDjxb/8fVEyhe9AVTBEeZwxIVXhvaMKJeRI5 A2Tf9J1ef4C8tT2vHYsUsmUGQzQECCOPdqWtI3oo7UlOID309rx9sbt2pzNv9GZQ4erb SBs9Oz0D3/vf4WzPLSwcBrmBvZ7v/i1x1sHbbnSeXi/pAAB7yox+0vM+O4s4Qx4vvcGE n0F217mDPzsg5Z6ZPW3YSslMefZAhyyfpRIsa4YfMq8H1gr6fg/gSelBmerFQzt7dm9k glEIQy18VKKuT9F2yatDj13HcHYVs1fVTUiNveGETW+roDCzTTMXRyXR1qKzpSeTY2Q6 dzKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=NQUFXWA6E8FIY5FfhI+SZs0H22qjLHwcDKCzPJiSIWg=; b=fkhVNz16/k3SUPd1eLiC1zxDuiOwacGbFfh2BmtWBO4/+m3q7Kyfc+X20F6HQueHF3 u66ngrT84r7cEFtFUuCJZuxoWw83bhWwO4e/Shxyn7SmnwpVpYXXWsqJE56m1TPFtQ35 BHuRnpn5qo5GzulWD5wM2WEgW+QlJHL81gxVTxG5ktLa+E0g19AJ125OAN81+YOw83DB Z2bjnvVoZY5p4zhqzwVnFxcCljluHb1bhiY/L/eIwLs8Mn+ClEZ2o+hlLmZ6eihz/JRB eRNHGPW+2OkWJZooVAGOd6H/nA+ouEO88dLI8fjOIU+qHG5j/rgZO2+XfU/z2k5k2eXK vwLw== X-Gm-Message-State: ANoB5plYs4GmRWfRWlqxOcwyHxlUrItYZEF534pEIO0YYL10qhuL4zSV d/QS2DTLr2jGqYfizDopkQw= X-Google-Smtp-Source: AA0mqf5GsRrlnEktRreEh+giwvvCZUekCJdnHp+uLJmH+qtRE/MpbBa/7+bap20QrA2FL0/MI5ABww== X-Received: by 2002:a17:902:e0cb:b0:18f:6cb:22ca with SMTP id e11-20020a170902e0cb00b0018f06cb22camr23852164pla.67.1671241694722; Fri, 16 Dec 2022 17:48:14 -0800 (PST) Received: from ?IPV6:2601:681:8600:13d0::f0a? ([2601:681:8600:13d0::f0a]) by smtp.gmail.com with ESMTPSA id 12-20020a170902c20c00b0018999a3dd7esm2269494pll.28.2022.12.16.17.48.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 16 Dec 2022 17:48:14 -0800 (PST) Message-ID: Date: Fri, 16 Dec 2022 18:48:13 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [PATCH] RISC-V: Fix RVV machine mode attribute configuration Content-Language: en-US To: juzhe.zhong@rivai.ai, gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com References: <20221214070156.37689-1-juzhe.zhong@rivai.ai> From: Jeff Law In-Reply-To: <20221214070156.37689-1-juzhe.zhong@rivai.ai> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 12/14/22 00:01, juzhe.zhong@rivai.ai wrote: > From: Ju-Zhe Zhong > > The attribute configuration of each machine mode are support in the previous patch. > I noticed some of them are not correct during VSETVL PASS testsing. > Correct them in the single patch now. > > gcc/ChangeLog: > > * config/riscv/riscv-vector-switch.def (ENTRY): Correct attributes. > > @@ -121,7 +121,7 @@ ENTRY (VNx2HI, true, LMUL_1, 16, LMUL_F2, 32) > ENTRY (VNx1HI, true, LMUL_F2, 32, LMUL_F4, 64) > > /* TODO:Disable all FP16 vector, enable them when 'zvfh' is supported. */ > -ENTRY (VNx32HF, false, LMUL_8, 2, LMUL_RESERVED, 0) > +ENTRY (VNx32HF, false, LMUL_RESERVED, 0, LMUL_8, 2) Is there any value in making VNx32HF dependent on TARGET_MIN_VLEN > 32 like we're doing for VNx32HI? In the past I've found it useful to have HI, HF, BF behave identically as much as possible. You call. The patch is OK either way. jeff