From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.ispras.ru (mail.ispras.ru [83.149.199.84]) by sourceware.org (Postfix) with ESMTPS id A3791383A63C for ; Mon, 30 May 2022 09:42:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A3791383A63C Received: from [10.10.3.121] (unknown [10.10.3.121]) by mail.ispras.ru (Postfix) with ESMTPS id 5BDD440D403D; Mon, 30 May 2022 09:41:57 +0000 (UTC) Date: Mon, 30 May 2022 12:41:57 +0300 (MSK) From: Alexander Monakov To: Hongtao Liu cc: "Liu, Hongtao" , "gcc-patches@gcc.gnu.org" Subject: Re: [PATCH] Add a bit dislike for separate mem alternative when op is REG_P. In-Reply-To: Message-ID: References: <20220525033920.77449-1-hongtao.liu@intel.com> <61cfc852-ed8e-1653-e94e-df5de7b3fc6f@ispras.ru> <84222b52-96f0-556e-6c14-6d3f5bd55ab@ispras.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 May 2022 09:42:02 -0000 On Mon, 30 May 2022, Hongtao Liu wrote: > On Mon, May 30, 2022 at 3:44 PM Alexander Monakov wrote: > > > > On Mon, 30 May 2022, Hongtao Liu wrote: > > > > > On Mon, May 30, 2022 at 2:22 PM Alexander Monakov via Gcc-patches > > > wrote: > > > > > > > > > > The spill is mainly decided by 3 insns related to r92 > > > > > > > > > > 283(insn 3 61 4 2 (set (reg/v:SF 92 [ x ]) > > > > > 284 (reg:SF 102)) "test3.c":7:1 142 {*movsf_internal} > > > > > 285 (expr_list:REG_DEAD (reg:SF 102) > > > > > > > > > > 288(insn 9 4 12 2 (set (reg:SI 89 [ _11 ]) > > > > > 289 (subreg:SI (reg/v:SF 92 [ x ]) 0)) "test3.c":3:36 81 {*movsi_internal} > > > > > 290 (nil)) > > > > > > > > > > And > > > > > 382(insn 28 27 29 5 (set (reg:DF 98) > > > > > 383 (float_extend:DF (reg/v:SF 92 [ x ]))) "test3.c":11:13 163 {*extendsfdf2} > > > > > 384 (expr_list:REG_DEAD (reg/v:SF 92 [ x ]) > > > > > 385 (nil))) > > > > > 386(insn 29 28 30 5 (s > > > > > > > > > > The frequency the for INSN 3 and INSN 9 is not affected, but frequency of INSN > > > > > 28 drop from 805 -> 89 after swapping "unlikely" and "likely". Because of > > > > > that, GPR cost decreases a lot, finally make the RA choose GPR instead of MEM. > > > > > > > > > > GENERAL_REGS:2356,2356 > > > > > SSE_REGS:6000,6000 > > > > > MEM:4089,4089 > > > > > > > > But why are SSE_REGS costed so high? r92 is used in SFmode, it doesn't make > > > > sense that selecting a GPR for it looks cheaper than xmm0. > > > For INSN3 and INSN 28, SSE_REGS costs zero. > > > But for INSN 9, it's a SImode move, we have disparaged non-gpr > > > alternatives in movsi_internal pattern which finally makes SSE_REGS > > > costs 6 * 1000(1000 is frequency, 6 is move cost between SSE_REGS and > > > GPR, sse_to_integer/integer_to_sse). > > > > But wait, selecting a GPR for r92 makes insn 3 (movsf_internal) an > > sse-to-integer move, so it should be equally high cost? Not to mention > > that the use in insn 28 (extendsfdf2) should have higher cost also. > > > > Why does GPR cost 2356 instead of 6000 for insn 3 plus extra for insn 28? > First GPR cost in insn 3 is not necessarily equal to integer_to_sse, > it's the minimal cost of all alternatives, and one alternative is ?r, > the cost is 2. > > I think the difference in movsf_internal and movsi_internal for *v and > ?r make RA finally choose GPR. I think this is one of the main issues here, if in the end it's the same 'mov %xmmN, ' instruction, only the pattern name is different. Alexander