From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 101460 invoked by alias); 6 Dec 2016 11:38:59 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 101437 invoked by uid 89); 6 Dec 2016 11:38:58 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.8 required=5.0 tests=BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=Best X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 06 Dec 2016 11:38:53 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 911901570; Tue, 6 Dec 2016 03:38:52 -0800 (PST) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B53E43F24D; Tue, 6 Dec 2016 03:38:51 -0800 (PST) Subject: Re: [PATCH, GCC/ARM, gcc-5/6-branch, ping] Fix PR77904: callee-saved register trashed when clobbering sp To: Kyrill Tkachov , Ramana Radhakrishnan , Richard Earnshaw References: <582C3541.5080308@foss.arm.com> <7921ba83-b881-8381-04ce-214f9440fc79@foss.arm.com> <582D7435.9090502@foss.arm.com> <7a70eca3-3442-2553-2434-08b5e00879a3@foss.arm.com> <7398e94c-acc6-7895-bd5d-c6ccfeaa29f0@foss.arm.com> Cc: "gcc-patches@gcc.gnu.org" From: Thomas Preudhomme Message-ID: Date: Tue, 06 Dec 2016 11:38:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 In-Reply-To: <7398e94c-acc6-7895-bd5d-c6ccfeaa29f0@foss.arm.com> Content-Type: multipart/mixed; boundary="------------C5C84413729055684A06E91F" X-IsSubscribed: yes X-SW-Source: 2016-12/txt/msg00440.txt.bz2 This is a multi-part message in MIME format. --------------C5C84413729055684A06E91F Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 2766 Ping? Best regards, Thomas On 30/11/16 10:44, Thomas Preudhomme wrote: > Sorry, the bug cannot be reproduced on gcc-5-branch so it's probably better to > only do a backport to gcc-6-branch. > > Ok for a backport to gcc-6-branch? > > Best regards, > > Thomas > > On 30/11/16 10:42, Thomas Preudhomme wrote: >> Hi, >> >> Is this ok to backport to gcc-5-branch and gcc-6-branch? Patch applies cleanly >> (patches attached for reference). >> >> >> 2016-11-30 Thomas Preud'homme >> >> Backport from mainline >> 2016-11-22 Thomas Preud'homme >> >> gcc/ >> PR target/77904 >> * config/arm/arm.c (thumb1_compute_save_reg_mask): Mark frame pointer >> in save register mask if it is needed. >> >> gcc/testsuite/ >> PR target/77904 >> * gcc.target/arm/pr77904.c: New test. >> >> >> Best regards, >> >> Thomas >> >> >> On 22/11/16 10:45, Thomas Preudhomme wrote: >>> On 17/11/16 09:11, Kyrill Tkachov wrote: >>>> >>>> On 17/11/16 08:56, Thomas Preudhomme wrote: >>>>> On 16/11/16 10:30, Kyrill Tkachov wrote: >>>>>> Hi Thomas, >>>>>> >>>>>> On 03/11/16 16:52, Thomas Preudhomme wrote: >>>>>>> Hi, >>>>>>> >>>>>>> When using a callee-saved register to save the frame pointer the Thumb-1 >>>>>>> prologue fails to save the callee-saved register before that. For ARM and >>>>>>> Thumb-2 targets the frame pointer is handled as a special case but >>>>>>> nothing is >>>>>>> done for Thumb-1 targets. This patch adds the same logic for Thumb-1 >>>>>>> targets. >>>>>>> >>>>>>> ChangeLog entries are as follow: >>>>>>> >>>>>>> *** gcc/ChangeLog *** >>>>>>> >>>>>>> 2016-11-02 Thomas Preud'homme >>>>>>> >>>>>>> PR target/77904 >>>>>>> * config/arm/arm.c (thumb1_compute_save_reg_mask): mark frame >>>>>>> pointer >>>>>>> in save register mask if it is needed. >>>>>>> >>>>>> >>>>>> s/mark/Mark/ >>>>>> >>>>>>> >>>>>>> *** gcc/testsuite/ChangeLog *** >>>>>>> >>>>>>> 2016-11-02 Thomas Preud'homme >>>>>>> >>>>>>> PR target/77904 >>>>>>> * gcc.target/arm/pr77904.c: New test. >>>>>>> >>>>>>> >>>>>>> Testing: Testsuite shows no regression when run with arm-none-eabi GCC >>>>>>> cross-compiler for Cortex-M0 target. >>>>>>> >>>>>>> Is this ok for trunk? >>>>>>> >>>>>> >>>>>> I'd ask for a bootstrap, but this code is Thumb-1 only so it wouldn't affect >>>>>> anything. >>>>> >>>>> I can bootstrap for armv4t with --with-mode=thumb which would at least >>>>> exercise the path. I'll try such a bootstrap on qemu. >>>>> >>>> >>>> If you can get it to work, then yes please. >>> >>> Bootstrap came back clean so I've committed the patch (r242693). Thanks! >>> >>> Best regards, >>> >>> Thomas --------------C5C84413729055684A06E91F Content-Type: text/x-patch; name="fix_ice_empty_fiq_handler_gcc6.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="fix_ice_empty_fiq_handler_gcc6.patch" Content-length: 2521 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 47171b99682207226aa4f9a76d4dfb54d6c2814b..86df1c0366be6c4b9b4ebf76821a8100c4e9fc16 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -575,9 +575,9 @@ ;; (plus (reg rN) (reg sp)) into (reg rN). In this case reload will ;; put the duplicated register first, and not try the commutative version. (define_insn_and_split "*arm_addsi3" - [(set (match_operand:SI 0 "s_register_operand" "=rk,l,l ,l ,r ,k ,r,r ,k ,r ,k,k,r ,k ,r") - (plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,k ,r,rk,k ,rk,k,r,rk,k ,rk") - (match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,rI,rI,k,Pj,Pj,L ,L,L,PJ,PJ,?n")))] + [(set (match_operand:SI 0 "s_register_operand" "=rk,l,l ,l ,r ,k ,r,k ,r ,k ,r ,k,k,r ,k ,r") + (plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,k ,r,r ,rk,k ,rk,k,r,rk,k ,rk") + (match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,rI,rI,k,rI,Pj,Pj,L ,L,L,PJ,PJ,?n")))] "TARGET_32BIT" "@ add%?\\t%0, %0, %2 @@ -587,6 +587,7 @@ add%?\\t%0, %1, %2 add%?\\t%0, %1, %2 add%?\\t%0, %2, %1 + add%?\\t%0, %1, %2 addw%?\\t%0, %1, %2 addw%?\\t%0, %1, %2 sub%?\\t%0, %1, #%n2 @@ -606,10 +607,10 @@ operands[1], 0); DONE; " - [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,16") + [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,4,16") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no") - (set_attr "arch" "t2,t2,t2,t2,*,*,*,t2,t2,*,*,a,t2,t2,*") + (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no,no") + (set_attr "arch" "t2,t2,t2,t2,*,*,*,a,t2,t2,*,*,a,t2,t2,*") (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") (const_string "alu_imm") (const_string "alu_sreg"))) diff --git a/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c b/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c new file mode 100644 index 0000000000000000000000000000000000000000..8313f2199122be153a737946e817a5e3bee60372 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { ! arm_cortex_m } { "-mthumb" } } */ + +/* Below code used to trigger an ICE due to missing constraints for + sp = fp + cst pattern. */ + +void fiq_handler (void) __attribute__((interrupt ("FIQ"))); + +void +fiq_handler (void) +{ +} --------------C5C84413729055684A06E91F--