* [PATCH] backport r257541, r259936, r260294, r260623, r261098, r261333, r268585.
@ 2019-04-04 7:49 luoxhu
2019-04-16 11:45 ` Segher Boessenkool
0 siblings, 1 reply; 4+ messages in thread
From: luoxhu @ 2019-04-04 7:49 UTC (permalink / raw)
To: gcc-patches; +Cc: segher, wschmidt, luoxhu, cel, seurer, Xiong Hu Luo
From: Xiong Hu Luo <luoxhu@linux.vnet.ibm.com>
These patches are followed changes for r255555 on testcases
vsx-vector-6*.c. backport them to update file names and fix regressions
for GCC7 on power9.
Regression tested on power7-be, power8-be, power8-le, power9.
gcc/ChangeLog:
2019-04-03 Xiong Hu Luo <luoxhu@linux.ibm.com>
backport from trunk r260623.
2018-05-23 Segher Boessenkool <segher@kernel.crashing.org>
* doc/sourcebuild.texi (Endianness): New subsubsection.
gcc/testsuite/ChangeLog:
2019-04-03 Xiong Hu Luo <luoxhu@linux.ibm.com>
backport from trunk r257541.
2018-02-07 Will Schmidt <will_schmidt@vnet.ibm.com>
* gcc.target/powerpc/vsx-vector-6-le.c: Update CPU target.
* gcc.target/powerpc/vsx-vector-6-le.p9.c: New.
backport from trunk r259936.
2018-05-04 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/vsx-vector-6.h (foo): Add test for vec_max,
vec_trunc.
* gcc.target/powerpc/vsx-vector-6-le.c (dg-final): Update xvcmpeqdp,
xvcmpgtdp, xvcmpgedp counts. Add xxsel counts.
* gcc.target/powerpc/vsx-vector-6-be.c (dg-final): Update xvcmpgtdp,
xvcmpgedp counts. Add xxsel counts.
backport from trunk r260294.
2018-05-16 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/vsx-vector-6-be.c: Remove file.
* gcc.target/powerpc/vsx-vector-6-be.p7.c: New test file.
* gcc.target/powerpc/vsx-vector-6-be.p8.c: New test file.
* gcc.target/powerpc/vsx-vector-6-le.c (dg-final): Update counts for
xvcmpeqdp., xvcmpgtdp., xvcmpgedp., xxlxor, xvrdpi.
backport from trunk r260623.
2018-05-23 Segher Boessenkool <segher@kernel.crashing.org>
* lib/target-supports.exp (check_effective_target_be): New.
(check_effective_target_le): New.
backport from part of trunk r261097.
2018-06-01 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/altivec-7-be.c: Delete file.
* gcc.target/powerpc/altivec-7-le.c: Delete file.
* gcc.target/powerpc/vsx-7-be.c: Remove file.
backport from trunk r261098.
2018-06-01 Carl Love <cel@us.ibm.com>
Commit 260294 on 2018-05-16 by Carl Love was supposed to add the
following files.
* gcc.target/powerpc/vsx-vector-6-be.p7.c: New test file.
* gcc.target/powerpc/vsx-vector-6-be.p8.c: New test file.
backport from trunk r261333.
2018-06-08 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/vsx-vector-6-be.p7.c: Rename this file to
vsx-vector-6.p7.c.
* gcc.target/powerpc/vsx-vector-6-le.p9.c: Rename this file to
vsx-vector-6.p9.c.
* gcc.target/powerpc/vsx-vector-6-be.p8.c: Move instruction counts
for BE system that are different then for an LE system from this file
into vsx-vector-6-le.c using be target qualifier. Remove this file.
* gcc.target/powerpc/vsx-vector-6-le.c: Add le qualifiers as needed for
the various instruction counts. Rename file to vsx-vector-6.p8.c.
backport from trunk r268585.
2019-02-06 Bill Seurer <seurer@linux.vnet.ibm.com>
* gcc.target/powerpc/vsx-vector-6.p7.c: Update instruction
counts and target.
* gcc.target/powerpc/vsx-vector-6.p8.c: Update instruction
counts and target.
* gcc.target/powerpc/vsx-vector-6.p9.c: Update instruction
counts and target.
---
gcc/doc/sourcebuild.texi | 10 ++++
gcc/testsuite/gcc.target/powerpc/altivec-7-be.c | 30 ------------
gcc/testsuite/gcc.target/powerpc/altivec-7-le.c | 37 ---------------
gcc/testsuite/gcc.target/powerpc/vsx-7-be.c | 50 --------------------
gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.c | 31 -------------
gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c | 32 -------------
gcc/testsuite/gcc.target/powerpc/vsx-vector-6.h | 14 +++++-
gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c | 42 +++++++++++++++++
gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c | 54 ++++++++++++++++++++++
gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c | 39 ++++++++++++++++
gcc/testsuite/lib/target-supports.exp | 16 +++++++
11 files changed, 173 insertions(+), 182 deletions(-)
delete mode 100644 gcc/testsuite/gcc.target/powerpc/altivec-7-be.c
delete mode 100644 gcc/testsuite/gcc.target/powerpc/altivec-7-le.c
delete mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-7-be.c
delete mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.c
delete mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index c7bb4b7..f0e9bb8 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -1273,6 +1273,16 @@ By convention, keywords ending in @code{_nocache} can also include options
specified for the particular test in an earlier @code{dg-options} or
@code{dg-add-options} directive.
+@subsubsection Endianness
+
+@table @code
+@item be
+Target uses big-endian memory order for multi-byte and multi-word data.
+
+@item le
+Target uses little-endian memory order for multi-byte and multi-word data.
+@end table
+
@subsubsection Data type sizes
@table @code
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7-be.c b/gcc/testsuite/gcc.target/powerpc/altivec-7-be.c
deleted file mode 100644
index 1e690be..0000000
--- a/gcc/testsuite/gcc.target/powerpc/altivec-7-be.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* { dg-do compile { target powerpc*-*-* } } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec" } */
-
-/* Expected results for Big Endian:
- vec_packpx vpkpx
- vec_ld lxvd2x
- vec_lde lvewx
- vec_ldl lxvl
- vec_lvewx lvewx
- vec_unpackh vupklsh
- vec_unpackl vupkhsh
- vec_andc xxnor
- xxland
- vec_vxor xxlxor
- vec_vmsumubm vmsumubm
- vec_vmulesb vmulesb
- vec_vmulosb vmulosb
-*/
-
-/* { dg-final { scan-assembler-times "vpkpx" 2 } } */
-/* { dg-final { scan-assembler-times "vmulesb" 1 } } */
-/* { dg-final { scan-assembler-times "vmulosb" 1 } } */
-/* { dg-final { scan-assembler-times "lvewx" 2 } } */
-/* { dg-final { scan-assembler-times "lvxl" 1 } } */
-/* { dg-final { scan-assembler-times "vupklsh" 1 } } */
-/* { dg-final { scan-assembler-times "vupkhsh" 1 } } */
-
-/* Source code for the test in altivec-7.h */
-#include "altivec-7.h"
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7-le.c b/gcc/testsuite/gcc.target/powerpc/altivec-7-le.c
deleted file mode 100644
index 50aab1c..0000000
--- a/gcc/testsuite/gcc.target/powerpc/altivec-7-le.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* { dg-do compile { target powerpc64le-*-* } } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec" } */
-
-/* Expected results for Little Endian:
- vec_packpx vpkpx
- vec_vmulosb vmulesb
- vec_ld lxv2x
- vec_lde lvewx
- vec_ldl lxvl
- vec_lvewx lvewx
- vec_unpackh vupklsh
- vec_unpackl vupkhsh
- vec_andc xxnor
- xxland
- vec_vxor xxlxor
- vec_vmsumubm vmsumubm
- vec_vmulesb vmulosb
- vec_vmulosb vmulesb
-*/
-
-/* { dg-final { scan-assembler-times "vpkpx" 2 } } */
-/* { dg-final { scan-assembler-times "vmulesb" 1 } } */
-/* { dg-final { scan-assembler-times "vmulosb" 1 } } */
-/* { dg-final { scan-assembler-times "lxvd2x" 33 } } */
-/* { dg-final { scan-assembler-times "lvewx" 2 } } */
-/* { dg-final { scan-assembler-times "lvxl" 1 } } */
-/* { dg-final { scan-assembler-times "vupklsh" 1 } } */
-/* { dg-final { scan-assembler-times "vupkhsh" 1 } } */
-/* { dg-final { scan-assembler-times "xxlnor" 0 } } */
-/* { dg-final { scan-assembler-times "xxland" 4 } } */
-/* { dg-final { scan-assembler-times "xxlxor" 5 } } */
-/* { dg-final { scan-assembler-times "vupkhpx" 1 } } */
-
-/* Source code for the test in altivec-7.h and vsx-7.h. */
-#include "altivec-7.h"
-#include "vsx-7.h"
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-7-be.c b/gcc/testsuite/gcc.target/powerpc/vsx-7-be.c
deleted file mode 100644
index 81230a0..0000000
--- a/gcc/testsuite/gcc.target/powerpc/vsx-7-be.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* { dg-do compile { target powerpc*-*-* } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-mvsx" } */
-
-/* This is an extension of altivec-7-be.c, with vsx target features included. */
-
-/* Expected results for Big Endian:
-(from altivec-7.h)
- vec_packpx vpkpx
- vec_ld lxvd2x or lxv
- vec_lde lvewx
- vec_ldl lxvl
- vec_lvewx lvewx
- vec_andc xxnor
- xxland
- vec_vxor xxlxor
- vec_vmsumubm vmsumubm
- vec_vmulesb vmulesb
- vec_vmulosb vmulosb
-(from vsx-7.h)
- vec_unpackl vupkhsh
- vec_unpackh vupklsh
-*/
-
-/* { dg-final { scan-assembler-times "vpkpx" 2 } } */
-/* { dg-final { scan-assembler-times "vmulesb" 1 } } */
-/* { dg-final { scan-assembler-times "vmulosb" 1 } } */
-
-// For LE platforms P9 and later, we generate the lxv insn instead of lxvd2x.
-/* { dg-final { scan-assembler-times {\mlxvd2x\M} 0 { target { { powerpc64*le-*-* } && { p9vector_hw } } } } } */
-/* { dg-final { scan-assembler-times {\mlxv\M} 36 { target { { powerpc64*le-*-* } && { p9vector_hw } } } } } */
-// For LE platforms < P9.
-/* { dg-final { scan-assembler-times {\mlxvd2x\M} 33 { target { { powerpc64*le-*-* } && { ! p9vector_hw } } } } } */
-// For BE platforms we generate 6 lxvd2x insns.
-/* { dg-final { scan-assembler-times {\mlxvd2x\M} 6 { target { { ! powerpc64*le-*-* } && { ! p9vector_hw } } } } } */
-
-/* { dg-final { scan-assembler-times "lvewx" 2 } } */
-/* { dg-final { scan-assembler-times "lvxl" 1 } } */
-/* { dg-final { scan-assembler-times "vupklsh" 1 } } */
-/* { dg-final { scan-assembler-times "vupkhsh" 1 } } */
-/* { dg-final { scan-assembler-times "xxlnor" 0 } } */
-/* { dg-final { scan-assembler-times "xxland" 4 } } */
-/* { dg-final { scan-assembler-times "xxlxor" 5 } } */
-/* { dg-final { scan-assembler-times "vupkhpx" 1 } } */
-
-/* Source code for the 'altivec' test in altivec-7.h */
-/* Source code for the 'vsx' required tests in vsx-7.h */
-
-#include "altivec-7.h"
-#include "vsx-7.h"
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.c
deleted file mode 100644
index a33f6d1..0000000
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* { dg-do compile { target { powerpc64-*-* && lp64 } } } */
-/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-mvsx -O2" } */
-
-/* Expected instruction counts for Big Endian */
-
-/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */
-/* { dg-final { scan-assembler-times "xvadddp" 1 } } */
-/* { dg-final { scan-assembler-times "xxlnor" 7 } } */
-/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 } } */
-/* { dg-final { scan-assembler-times "xvcmpgtdp" 7 } } */
-/* { dg-final { scan-assembler-times "xvcmpgedp" 6 } } */
-/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */
-/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */
-/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */
-/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */
-/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */
-/* { dg-final { scan-assembler-times "xvmindp" 1 } } */
-/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */
-/* { dg-final { scan-assembler-times "vperm" 1 } } */
-/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */
-/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */
-/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */
-/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */
-/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */
-/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */
-/* { dg-final { scan-assembler-times "xxland" 13 } } */
-
-/* Source code for the test in vsx-vector-6.h */
-#include "vsx-vector-6.h"
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c
deleted file mode 100644
index b734761..0000000
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* { dg-do compile { target { powerpc64le-*-* && lp64 } } } */
-/* { dg-skip-if "" { powerpc*-*-darwin* } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-mvsx -O2" } */
-
-/* Expected instruction counts for Little Endian */
-
-/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */
-/* { dg-final { scan-assembler-times "xvadddp" 1 } } */
-/* { dg-final { scan-assembler-times "xxlnor" 6 } } */
-/* { dg-final { scan-assembler-times "xxlor" 14 } } */
-/* { dg-final { scan-assembler-times "xvcmpeqdp" 5 } } */
-/* { dg-final { scan-assembler-times "xvcmpgtdp" 7 } } */
-/* { dg-final { scan-assembler-times "xvcmpgedp" 6 } } */
-/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */
-/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */
-/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */
-/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */
-/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */
-/* { dg-final { scan-assembler-times "xvmindp" 1 } } */
-/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */
-/* { dg-final { scan-assembler-times "vperm" 1 } } */
-/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */
-/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */
-/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */
-/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */
-/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */
-/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */
-/* { dg-final { scan-assembler-times "xxland" 9 } } */
-
-/* Source code for the test in vsx-vector-6.h */
-#include "vsx-vector-6.h"
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.h b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.h
index 422f8a1..a891b64 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.h
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.h
@@ -7,7 +7,9 @@
void foo (vector double *out, vector double *in, vector long *p_l, vector bool long *p_b,
vector unsigned char *p_uc, int *i, vector float *p_f,
vector bool char *outbc, vector bool int *outbi,
- vector bool short *outbsi, vector int *outsi, vector unsigned int *outui)
+ vector bool short *outbsi, vector int *outsi,
+ vector unsigned int *outui, vector signed char *outsc,
+ vector unsigned char *outuc)
{
vector double in0 = in[0];
vector double in1 = in[1];
@@ -20,6 +22,8 @@ void foo (vector double *out, vector double *in, vector long *p_l, vector bool l
vector float inf0;
vector float inf1;
vector float inf2;
+ vector char inc0;
+ vector char inc1;
vector bool char inbc0;
vector bool char inbc1;
vector bool short inbs0;
@@ -30,6 +34,7 @@ void foo (vector double *out, vector double *in, vector long *p_l, vector bool l
vector unsigned short int inusi0, inusi1;
vector signed int insi0, insi1;
vector unsigned int inui0, inui1;
+ vector unsigned char inuc0, inuc1;
*out++ = vec_abs (in0);
*out++ = vec_add (in0, in1);
@@ -103,6 +108,7 @@ void foo (vector double *out, vector double *in, vector long *p_l, vector bool l
*p_f++ = vec_nmsub (inf0, inf1, inf2);
*p_f++ = vec_nmadd (inf0, inf1, inf2);
*p_f++ = vec_or (inf0, inf1);
+ *p_f++ = vec_trunc (inf0);
*out++ = vec_or (inbl0, in0);
*out++ = vec_or (in0, inbl0);
@@ -113,6 +119,8 @@ void foo (vector double *out, vector double *in, vector long *p_l, vector bool l
*outbc++ = vec_andc (inbc0, inbc1);
*outbc++ = vec_or (inbc0, inbc1);
+ *outuc++ = vec_max (inuc0, inuc1);
+
*outbi++ = vec_andc (inbi0, inbi1);
*outbsi++ = vec_andc (inbs0, inbs1);
@@ -151,7 +159,9 @@ int main()
vector bool short *outbsi;
vector int *outsi;
vector unsigned int *outui;
+ vector signed char *outsc;
+ vector unsigned char *outuc;
foo (out, in, p_l, p_b, p_uc, i, p_f, outbc,
- outbi, outbsi, outsi, outui);
+ outbi, outbsi, outsi, outui, outsc, outuc);
}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c
new file mode 100644
index 0000000..68f40db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c
@@ -0,0 +1,42 @@
+/* { dg-do compile { target { lp64 && be } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx -O2 -mcpu=power7 -dp" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
+
+/* Expected instruction counts for Power 7 */
+
+/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvadddp" 1 } } */
+/* { dg-final { scan-assembler-times "xxlnor" 5 } } */
+/* { dg-final { scan-assembler-times {\mxvcmpeqdp\s} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvcmpeqdp\.\s} 5 } } */
+/* { dg-final { scan-assembler-times {\mxvcmpgtdp\s} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvcmpgtdp\.\s} 5 } } */
+/* { dg-final { scan-assembler-times {\mxvcmpgedp\s} 1 } } */
+/* { dg-final { scan-assembler-times {\mxvcmpgedp\.\s} 6 } } */
+/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */
+/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */
+/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmindp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */
+/* { dg-final { scan-assembler-times "vperm" 2 } } */
+/* { dg-final { scan-assembler-times "xvrdpic" 2 } } */
+/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */
+/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */
+/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */
+/* { dg-final { scan-assembler-times "xvnmaddadp" 1 } } */
+/* { dg-final { scan-assembler-times "xvnmsubadp" 1 } } */
+/* { dg-final { scan-assembler-times "vmsumshs" 2 } } */
+/* { dg-final { scan-assembler-times "xxland" 13 } } */
+/* { dg-final { scan-assembler-times "xxlxor" 2 } } */
+/* { dg-final { scan-assembler-times "xxsel" 4 } } */
+/* { dg-final { scan-assembler-times "xvrdpip" 1 } } */
+/* { dg-final { scan-assembler-times "xvdivdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvrdpi" 7 } } */
+
+/* Source code for the test in vsx-vector-6.h */
+#include "vsx-vector-6.h"
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c
new file mode 100644
index 0000000..5edff4e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c
@@ -0,0 +1,54 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx -O2 -mcpu=power8" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+
+/* Expected instruction counts for Power 8. */
+
+/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvadddp" 1 } } */
+/* { dg-final { scan-assembler-times "xxlnor" 6 { target le } } } */
+/* { dg-final { scan-assembler-times "xxlnor" 5 { target be } } } */
+
+/* We generate xxlor instructions for many reasons other than or'ing vector
+ operands or calling __builtin_vec_or(), which means we cannot rely on
+ their usage counts being stable. Therefore, we just ensure at least one
+ xxlor instruction was generated. */
+/* { dg-final { scan-assembler "xxlor" } } */
+
+/* { dg-final { scan-assembler-times {\mxvcmpeqdp\s} 0 { target le } } } */
+/* { dg-final { scan-assembler-times {\mxvcmpeqdp\s} 1 { target be } } } */
+/* { dg-final { scan-assembler-times {\mxvcmpeqdp\.\s} 6 { target le } } } */
+/* { dg-final { scan-assembler-times {\mxvcmpeqdp\.\s} 5 { target be } } } */
+/* { dg-final { scan-assembler-times {\mxvcmpgtdp\s} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvcmpgtdp\.\s} 5 { target le } } } */
+/* { dg-final { scan-assembler-times {\mxvcmpgtdp\.\s} 6 { target le } } } */
+/* { dg-final { scan-assembler-times {\mxvcmpgedp\s} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvcmpgedp\.\s} 4 } } */
+/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */
+/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */
+/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmindp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */
+/* { dg-final { scan-assembler-times "vperm" 1 } } */
+/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */
+/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */
+/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */
+/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */
+/* { dg-final { scan-assembler-times "xvnmaddadp" 1 } } */
+/* { dg-final { scan-assembler-times "xvnmsubadp" 1 } } */
+/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */
+/* { dg-final { scan-assembler-times "xxland" 9 { target le } } } */
+/* { dg-final { scan-assembler-times "xxland" 13 { target be } } } */
+/* { dg-final { scan-assembler-times "xxlxor" 2 } } */
+/* { dg-final { scan-assembler-times "xxsel" 2 } } */
+/* { dg-final { scan-assembler-times "xvrdpip" 1 } } */
+/* { dg-final { scan-assembler-times "xvdivdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvrdpi" 5 } } */
+
+/* Source code for the test in vsx-vector-6.h */
+#include "vsx-vector-6.h"
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c
new file mode 100644
index 0000000..48ac4a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c
@@ -0,0 +1,39 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mvsx -O2 -mcpu=power9" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+
+/* Expected instruction counts for Power9. */
+
+/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvadddp" 1 } } */
+/* { dg-final { scan-assembler-times "xxlnor" 5 } } */
+
+/* We generate xxlor instructions for many reasons other than or'ing vector
+ operands or calling __builtin_vec_or(), which means we cannot rely on
+ their usage counts being stable. Therefore, we just ensure at least one
+ xxlor instruction was generated. */
+/* { dg-final { scan-assembler "xxlor" } } */
+
+/* { dg-final { scan-assembler-times "xvcmpeqdp" 7 } } */
+/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 } } */
+/* { dg-final { scan-assembler-times "xvcmpgedp" 7 } } */
+/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */
+/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */
+/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmindp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */
+/* { dg-final { scan-assembler-times "vperm" 1 } } */
+/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */
+/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */
+/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */
+/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */
+/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */
+/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */
+/* { dg-final { scan-assembler-times "xxland" 13 } } */
+
+/* Source code for the test in vsx-vector-6.h */
+#include "vsx-vector-6.h"
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index f08535d..546edfd 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2365,6 +2365,22 @@ proc check_effective_target_next_runtime { } {
}]
}
+# Return 1 if we're generating code for big-endian memory order.
+
+proc check_effective_target_be { } {
+ return [check_no_compiler_messages be object {
+ int dummy[__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ ? 1 : -1];
+ }]
+}
+
+# Return 1 if we're generating code for little-endian memory order.
+
+proc check_effective_target_le { } {
+ return [check_no_compiler_messages le object {
+ int dummy[__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ ? 1 : -1];
+ }]
+}
+
# Return 1 if we're generating 32-bit code using default options, 0
# otherwise.
--
2.7.4
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] backport r257541, r259936, r260294, r260623, r261098, r261333, r268585.
2019-04-04 7:49 [PATCH] backport r257541, r259936, r260294, r260623, r261098, r261333, r268585 luoxhu
@ 2019-04-16 11:45 ` Segher Boessenkool
2019-04-17 7:10 ` Xiong Hu Luo
0 siblings, 1 reply; 4+ messages in thread
From: Segher Boessenkool @ 2019-04-16 11:45 UTC (permalink / raw)
To: luoxhu; +Cc: gcc-patches, wschmidt, cel, seurer, Xiong Hu Luo
Hi Xiong,
Sorry I took so long to review this.
On Thu, Apr 04, 2019 at 02:49:29AM -0500, luoxhu@linux.ibm.com wrote:
> These patches are followed changes for r255555 on testcases
> vsx-vector-6*.c. backport them to update file names and fix regressions
> for GCC7 on power9.
(See e.g. https://gcc.gnu.org/ml/gcc-testresults/2019-04/msg01868.html for
the failures this patch fixes; the patch is for GCC 7).
> gcc/ChangeLog:
>
> 2019-04-03 Xiong Hu Luo <luoxhu@linux.ibm.com>
>
> backport from trunk r260623.
>
> 2018-05-23 Segher Boessenkool <segher@kernel.crashing.org>
>
> * doc/sourcebuild.texi (Endianness): New subsubsection.
We write the changelog like
2019-04-16 Xiong Hu Luo <luoxhu@linux.ibm.com>
Backport from trunk
2018-05-23 Segher Boessenkool <segher@kernel.crashing.org>
* doc/sourcebuild.texi (Endianness): New subsubsection.
(no revision number, capital on Backport, no empty line after it).
> 2019-04-03 Xiong Hu Luo <luoxhu@linux.ibm.com>
>
> backport from trunk r257541.
>
> 2018-02-07 Will Schmidt <will_schmidt@vnet.ibm.com>
>
> * gcc.target/powerpc/vsx-vector-6-le.c: Update CPU target.
> * gcc.target/powerpc/vsx-vector-6-le.p9.c: New.
Only one space after : please.
> 2018-05-04 Carl Love <cel@us.ibm.com>
Two spaces between date and name.
> * gcc.target/powerpc/vsx-vector-6-le.c: Add le qualifiers as needed for
> the various instruction counts. Rename file to vsx-vector-6.p8.c.
There's a tab after "to" here, should be a space.
Other than those nits, okay for the GCC 7 branch, thanks!
("be" and "le" are essentially PowerPC-specific selectors on the 7 branch,
otherwise you'd need a release manager's approval as well).
Segher
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] backport r257541, r259936, r260294, r260623, r261098, r261333, r268585.
2019-04-16 11:45 ` Segher Boessenkool
@ 2019-04-17 7:10 ` Xiong Hu Luo
2019-04-17 17:45 ` Segher Boessenkool
0 siblings, 1 reply; 4+ messages in thread
From: Xiong Hu Luo @ 2019-04-17 7:10 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: gcc-patches, wschmidt, cel, seurer, Xiong Hu Luo
Hi Segher,
On 2019/4/16 PM6:54, Segher Boessenkool wrote:
> Hi Xiong,
>
> Sorry I took so long to review this.
>
> On Thu, Apr 04, 2019 at 02:49:29AM -0500, luoxhu@linux.ibm.com wrote:
>> These patches are followed changes for r255555 on testcases
>> vsx-vector-6*.c. backport them to update file names and fix regressions
>> for GCC7 on power9.
>
> (See e.g. https://gcc.gnu.org/ml/gcc-testresults/2019-04/msg01868.html for
> the failures this patch fixes; the patch is for GCC 7).
>
>> gcc/ChangeLog:
>>
>> 2019-04-03 Xiong Hu Luo <luoxhu@linux.ibm.com>
>>
>> backport from trunk r260623.
>>
>> 2018-05-23 Segher Boessenkool <segher@kernel.crashing.org>
>>
>> * doc/sourcebuild.texi (Endianness): New subsubsection.
>
> We write the changelog like
>
> 2019-04-16 Xiong Hu Luo <luoxhu@linux.ibm.com>
>
> Backport from trunk
> 2018-05-23 Segher Boessenkool <segher@kernel.crashing.org>
>
> * doc/sourcebuild.texi (Endianness): New subsubsection.
>
> (no revision number, capital on Backport, no empty line after it).
>
>> 2019-04-03 Xiong Hu Luo <luoxhu@linux.ibm.com>
>>
>> backport from trunk r257541.
>>
>> 2018-02-07 Will Schmidt <will_schmidt@vnet.ibm.com>
>>
>> * gcc.target/powerpc/vsx-vector-6-le.c: Update CPU target.
>> * gcc.target/powerpc/vsx-vector-6-le.p9.c: New.
>
> Only one space after : please.
>
>> 2018-05-04 Carl Love <cel@us.ibm.com>
>
> Two spaces between date and name.
>
>> * gcc.target/powerpc/vsx-vector-6-le.c: Add le qualifiers as needed for
>> the various instruction counts. Rename file to vsx-vector-6.p8.c.
>
> There's a tab after "to" here, should be a space.
>
>
> Other than those nits, okay for the GCC 7 branch, thanks!
I will modify all the ChangeLog nits by copy-paste, thanks.
>
> ("be" and "le" are essentially PowerPC-specific selectors on the 7 branch,
> otherwise you'd need a release manager's approval as well).
Do you mean move the "be" and "le" code from
gcc/testsuite/lib/target-supports.exp to
gcc/testsuite/gcc.target/powerpc/powerpc.exp here? I tried this, it can
work.
This require ChangeLog update as below? Or rewrite all the ChangeLog
with mine signed-of-by?
2018-05-23 Segher Boessenkool <segher@kernel.crashing.org>
* lib/target-supports.exp (check_effective_target_be): New.
(check_effective_target_le): New.
=>
2018-05-23 Segher Boessenkool <segher@kernel.crashing.org>
* gcc.target/powerpc/powerpc.exp
(check_effective_target_be): New.
(check_effective_target_le): New.
Also need update the "doc/sourcebuild.texi" from "+@subsubsection
Endianness" to "+@subsubsection Endianness For powerpc".
Thanks
Xiong Hu
>
>
> Segher
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] backport r257541, r259936, r260294, r260623, r261098, r261333, r268585.
2019-04-17 7:10 ` Xiong Hu Luo
@ 2019-04-17 17:45 ` Segher Boessenkool
0 siblings, 0 replies; 4+ messages in thread
From: Segher Boessenkool @ 2019-04-17 17:45 UTC (permalink / raw)
To: Xiong Hu Luo; +Cc: gcc-patches, wschmidt, cel, seurer, Xiong Hu Luo
Hi!
On Wed, Apr 17, 2019 at 03:05:06PM +0800, Xiong Hu Luo wrote:
> On 2019/4/16 PM6:54, Segher Boessenkool wrote:
> > ("be" and "le" are essentially PowerPC-specific selectors on the 7 branch,
> > otherwise you'd need a release manager's approval as well).
>
> Do you mean move the "be" and "le" code from
> gcc/testsuite/lib/target-supports.exp to
> gcc/testsuite/gcc.target/powerpc/powerpc.exp here?
I mean it is okay as you posted it, and I can approve it even though it
is in generic code.
:-)
Segher
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-04-17 17:16 UTC | newest]
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2019-04-04 7:49 [PATCH] backport r257541, r259936, r260294, r260623, r261098, r261333, r268585 luoxhu
2019-04-16 11:45 ` Segher Boessenkool
2019-04-17 7:10 ` Xiong Hu Luo
2019-04-17 17:45 ` Segher Boessenkool
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