Re: [PATCH] RISC-V: Support highest-number regno overlap for widen ternary vx instructions

[Robin Dapp <rdapp.gcc@gmail.com>]

> +(define_mode_attr widen_ternop_dest_constraint [
> +  (RVVM8QI "=vd, vr, vd, vr, vd, vr, ?&vr")
> +  (RVVM4QI "=vd, vr, vd, vr, vd, vr, ?&vr")
> +  (RVVM2QI "=vd, vr, vd, vr, vd, vr, ?&vr")
> +  (RVVM1QI "=vd, vr, vd, vr, vd, vr, ?&vr")
> +  (RVVMF2QI "=vd, vr, vd, vr, vd, vr, ?&vr")
> +  (RVVMF4QI "=vd, vr, vd, vr, vd, vr, ?&vr")
> +  (RVVMF8QI "=vd, vr, vd, vr, vd, vr, ?&vr")
> +  (RVVM8HI "=vd, vr, vd, vr, vd, vr, ?&vr")
[...]

I'm fine with avoiding the overlap but I'm not sure this is
easily maintainable because the constraints don't actually
depend on the mode?  I suppose this is for easy re-use across
different insns but there are only six(?) widening patterns
so we don't even save lines of code by this?

I guess I would prefer the normal approach of writing it out
explicitly in the pattern.  Maybe add a different replacement
method like define_subst in the future to simplify such
situations?


+  "vwmacc<u>.vx\t%0,%z3,%4%p1"

Why the z here?  For canonicalization?

Regards
 Robin