From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 15266 invoked by alias); 17 Sep 2019 11:25:05 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 15246 invoked by uid 89); 17 Sep 2019 11:25:05 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-4.2 required=5.0 tests=AWL,BAYES_50,KAM_NUMSUBJECT autolearn=no version=3.3.1 spammy=1794, 991, rvae1isx0, Shaokun X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 17 Sep 2019 11:25:03 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1E4481570; Tue, 17 Sep 2019 04:25:02 -0700 (PDT) Received: from [10.2.206.47] (e120808-lin.cambridge.arm.com [10.2.206.47]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 34D543F774; Tue, 17 Sep 2019 04:25:01 -0700 (PDT) Subject: Re: [Question on aarch64] Questions on TLB range instructions on aarch64 To: Shaokun Zhang , "gcc-patches@gcc.gnu.org" Cc: Richard Earnshaw , James Greenhalgh , Marcus Shawcroft , Richard Sandiford , "Tangnianyao (ICT)" References: From: Kyrill Tkachov Message-ID: Date: Tue, 17 Sep 2019 11:25:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-SW-Source: 2019-09/txt/msg00994.txt.bz2 Hi Shaokun, On 9/17/19 12:17 PM, Shaokun Zhang wrote: > Hi aarch64 maintainers, > > Sorry to noise you again. > No problem :) However, this isn't strictly-speaking a gcc issue because... > We(HiSilicon) next generation CPU core will support "ARMv8.4-TLBI, TLB > maintenance and TLB range instructions" > feature, so I try to compile it that tlbi rvae1is is replaced in linux > kernel which is in my local branch, > there are some error messages: > > /tmp/ccD5TFDe.s: Assembler messages: > /tmp/ccD5TFDe.s:991: Error: unknown or missing operation name at > operand 1 -- `tlbi rvae1is,x0' > /tmp/ccD5TFDe.s:1012: Error: unknown or missing operation name at > operand 1 -- `tlbi rvae1is,x0' > /tmp/ccD5TFDe.s:1794: Error: unknown or missing operation name at > operand 1 -- `tlbi rvae1is,x0' > /tmp/ccD5TFDe.s:1815: Error: unknown or missing operation name at > operand 1 -- `tlbi rvae1is,x0' > /tmp/ccD5TFDe.s:2398: Error: unknown or missing operation name at > operand 1 -- `tlbi rvae1is,x0' > /tmp/ccD5TFDe.s:2419: Error: unknown or missing operation name at > operand 1 -- `tlbi rvae1is,x0' > /tmp/ccD5TFDe.s:3155: Error: unknown or missing operation name at > operand 1 -- `tlbi rvae1is,x0' > /tmp/ccD5TFDe.s:3176: Error: unknown or missing operation name at > operand 1 -- `tlbi rvae1is,x0' > /tmp/ccD5TFDe.s:1016: Error: attempt to move .org backwards > /tmp/ccD5TFDe.s:1819: Error: attempt to move .org backwards > /tmp/ccD5TFDe.s:2423: Error: attempt to move .org backwards > /tmp/ccD5TFDe.s:3180: Error: attempt to move .org backwards > make[2]: *** [arch/arm64/mm/hugetlbpage.o] Error 1 > make[1]: *** [arch/arm64/mm] Error 2 > make: *** [sub-make] Error 2 > ... These are assembler messages from gas. These system registers should be supported in more recent binutils versions. They were added with https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=793a194839bc8add71fdc7429c58b10f0667a6f6 I suggest you update your binutils to a later version to get the support. Thanks, Kyrill > GCC version is as follow: > gcc (GCC) 9.2.0 > Copyright (C) 2019 Free Software Foundation, Inc. > This is free software; see the source for copying conditions.  There is NO > warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR > PURPOSE. > > It seems that GCC doesn't support this new instruction and I checked > that LLVM has already supported > this instruction, > https://github.com/llvm-mirror/llvm/blob/master/lib/Target/AArch64/AArch64SystemOperands.td > > So my question is that does GCC have the plan to support this > instruction recently? > If not, can you give me some suggestion to do it? I'm not the expert > on it  ;-) > > Thanks in advance, > Shaokun >