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([2601:681:8600:13d0::f0a]) by smtp.gmail.com with ESMTPSA id bt20-20020a17090af01400b00246cfdb570asm16226pjb.27.2023.04.18.14.04.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Apr 2023 14:04:23 -0700 (PDT) Message-ID: Date: Tue, 18 Apr 2023 15:04:22 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH v5] RISCV: Inline subword atomic ops Content-Language: en-US To: Patrick O'Neill , gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, kito.cheng@gmail.com, david.abd@gmail.com References: <20220821215823.18207-1-palmer@rivosinc.com> <20230418142858.2424851-1-patrick@rivosinc.com> From: Jeff Law In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 4/18/23 14:48, Patrick O'Neill wrote: > On 4/18/23 09:59, Jeff Law wrote: >> On 4/18/23 08:28, Patrick O'Neill wrote: >> ... >>> +  rtx addr = force_reg (Pmode, XEXP (mem, 0)); >>> + >>> +  rtx aligned_addr = gen_reg_rtx (Pmode); >>> +  emit_move_insn (aligned_addr,  gen_rtx_AND (Pmode, addr, >>> +                          gen_int_mode (-4, Pmode))); >> So rather than -4 as a magic number, GET_MODE_MASK would be better. >> That may result in needing to rewrap this code.  I'd bring the >> gen_rtx_AND down on a new line, aligned with aligned_addr. > IIUC GET_MODE_MASK generates masks like 0xFF for QI (for example). It > doesn't have the granularity to generate 0x3 (which we can NOT to get > -4). I searched the GCC internals docs but couldn't find a function that > does address alignment masks. Yea, yea. Big "duh" on my side. >> Presumably using SImode is intentional here rather than wanting to use >> word_mode which would be SImode for rv32 and DImode for rv64?  I'm >> going to work based on that assumption, but if it isn't there's more >> work to do to generalize this code. > It's been a year but IIRC it was just simpler to implement (and to me it > didn't make sense to use 64 bits for a subword op). > Is there a benefit in using 64 bit instructions when computing subwords? Given that rv64 should have 32bit load/stores, I don't offhand see any advantage. >>> + >>> +(define_expand "atomic_fetch_nand" >>> +  [(set (match_operand:SHORT 0 "register_operand" "=&r") >>> +    (match_operand:SHORT 1 "memory_operand" "+A")) >>> +   (set (match_dup 1) >>> +    (unspec_volatile:SHORT >>> +      [(not:SHORT (and:SHORT (match_dup 1) >>> +                 (match_operand:SHORT 2 "reg_or_0_operand" "rJ"))) >>> +       (match_operand:SI 3 "const_int_operand")] ;; model >>> +     UNSPEC_SYNC_OLD_OP_SUBWORD))] >>> +  "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" >> Just a note, constraints aren't necessary for a define_expand. They >> don't hurt anything though.  They do document expectations, but then >> you have to maintain them over time.  I'm OK leaving them, mostly >> wanted to make sure you're aware they aren't strictly necessary for a >> define_expand. > I wasn't aware, thanks for pointing it out! - you're referring to the > "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC", (not the register > constraints) right? I was referring to the register constraints like "=&r". They're ignored on define_expand constructors. A define_expand generates RTL that will be matched later by a define_insn. The "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" is usually referred to as the insn condition. > Thanks for reviewing! NP. Looking forward to V6 which I expect will be ready for inclusion. jeff