[PATCH] rs6000: MMA builtin usage ICEs when used in a #pragma omp parallel and using -fopenmp [PR100777]

[Peter Bergner <bergner@linux.ibm.com>]

Using an MMA builtin within an openmp parallel code block leads to an SSA
verification ICE on the temporaries we create while expanding the MMA builtins
at gimple time.  The solution is to use create_tmp_reg_or_ssa_name(), which
knows when to create either an SSA or register temporary.

This fixes the ICE and bootstraps and regtests with no regressions.
Ok for trunk?

The same ICE occurs in GCC 11 and GCC 10.  Ok to backport to those release
branches after some burn in on trunk?

Peter


gcc/
	PR target/100777
	* config/rs6000/rs6000-call.c (rs6000_gimple_fold_mma_builtin): Use
	create_tmp_reg_or_ssa_name().

gcc/testsuite/
	PR target/100777
	* gcc.target/powerpc/pr100777.c: New test.

diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
index f271b0a4079..5eab4fa1ce3 100644
--- a/gcc/config/rs6000/rs6000-call.c
+++ b/gcc/config/rs6000/rs6000-call.c
@@ -11724,7 +11724,7 @@ rs6000_gimple_fold_mma_builtin (gimple_stmt_iterator *gsi)
       tree dst_ptr = gimple_call_arg (stmt, 0);
       tree src_ptr = gimple_call_arg (stmt, 1);
       tree src_type = TREE_TYPE (src_ptr);
-      tree src = make_ssa_name (TREE_TYPE (src_type));
+      tree src = create_tmp_reg_or_ssa_name (TREE_TYPE (src_type));
       gimplify_assign (src, build_simple_mem_ref (src_ptr), &new_seq);
 
       /* If we are not disassembling an accumulator/pair or our destination is
@@ -11748,7 +11748,7 @@ rs6000_gimple_fold_mma_builtin (gimple_stmt_iterator *gsi)
 	{
 	  new_decl = rs6000_builtin_decls[MMA_BUILTIN_XXMFACC_INTERNAL];
 	  new_call = gimple_build_call (new_decl, 1, src);
-	  src = make_ssa_name (vector_quad_type_node);
+	  src = create_tmp_reg_or_ssa_name (vector_quad_type_node);
 	  gimple_call_set_lhs (new_call, src);
 	  gimple_seq_add_stmt (&new_seq, new_call);
 	}
@@ -11763,7 +11763,7 @@ rs6000_gimple_fold_mma_builtin (gimple_stmt_iterator *gsi)
 	  unsigned index = WORDS_BIG_ENDIAN ? i : nvec - 1 - i;
 	  tree dst = build2 (MEM_REF, unsigned_V16QI_type_node, dst_base,
 			     build_int_cst (dst_type, index * 16));
-	  tree dstssa = make_ssa_name (unsigned_V16QI_type_node);
+	  tree dstssa = create_tmp_reg_or_ssa_name (unsigned_V16QI_type_node);
 	  new_call = gimple_build_call (new_decl, 2, src,
 					build_int_cstu (uint16_type_node, i));
 	  gimple_call_set_lhs (new_call, dstssa);
@@ -11786,7 +11786,7 @@ rs6000_gimple_fold_mma_builtin (gimple_stmt_iterator *gsi)
     {
       /* This built-in has a pass-by-reference accumulator input, so load it
 	 into a temporary accumulator for use as a pass-by-value input.  */
-      op[0] = make_ssa_name (vector_quad_type_node);
+      op[0] = create_tmp_reg_or_ssa_name (vector_quad_type_node);
       for (unsigned i = 1; i < nopnds; i++)
 	op[i] = gimple_call_arg (stmt, i);
       gimplify_assign (op[0], build_simple_mem_ref (acc), &new_seq);
@@ -11834,9 +11834,9 @@ rs6000_gimple_fold_mma_builtin (gimple_stmt_iterator *gsi)
     }
 
   if (fncode == VSX_BUILTIN_ASSEMBLE_PAIR)
-    lhs = make_ssa_name (vector_pair_type_node);
+    lhs = create_tmp_reg_or_ssa_name (vector_pair_type_node);
   else
-    lhs = make_ssa_name (vector_quad_type_node);
+    lhs = create_tmp_reg_or_ssa_name (vector_quad_type_node);
   gimple_call_set_lhs (new_call, lhs);
   gimple_seq_add_stmt (&new_seq, new_call);
   gimplify_assign (build_simple_mem_ref (acc), lhs, &new_seq);
diff --git a/gcc/testsuite/gcc.target/powerpc/pr100777.c b/gcc/testsuite/gcc.target/powerpc/pr100777.c
new file mode 100644
index 00000000000..15742f67d8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr100777.c
@@ -0,0 +1,24 @@
+/* PR target/100777 */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target fopenmp } */
+/* { dg-options "-O1 -mdejagnu-cpu=power10 -fopenmp" } */
+
+/* Verify we do not ICE on the following.  */
+
+void
+foo (__vector_quad *dst)
+{
+#pragma omp parallel
+  {
+    __builtin_mma_xxsetaccz (dst);
+  }
+}
+
+void
+bar (__vector_quad *dst, __vector_quad *src)
+{
+#pragma omp parallel
+  {
+    __builtin_mma_disassemble_acc (dst, src);
+  }
+}