From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 495F3385C405 for ; Wed, 28 Jul 2021 20:38:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 495F3385C405 Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 16SK36V2113522; Wed, 28 Jul 2021 16:38:38 -0400 Received: from ppma03wdc.us.ibm.com (ba.79.3fa9.ip4.static.sl-reverse.com [169.63.121.186]) by mx0a-001b2d01.pphosted.com with ESMTP id 3a38tf2vjp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 28 Jul 2021 16:38:37 -0400 Received: from pps.filterd (ppma03wdc.us.ibm.com [127.0.0.1]) by ppma03wdc.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 16SKKPMo031488; Wed, 28 Jul 2021 20:38:36 GMT Received: from b03cxnp08028.gho.boulder.ibm.com (b03cxnp08028.gho.boulder.ibm.com [9.17.130.20]) by ppma03wdc.us.ibm.com with ESMTP id 3a235p28jw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 28 Jul 2021 20:38:36 +0000 Received: from b03ledav003.gho.boulder.ibm.com (b03ledav003.gho.boulder.ibm.com [9.17.130.234]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 16SKcZWc13959522 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 28 Jul 2021 20:38:35 GMT Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3434E6A05F; Wed, 28 Jul 2021 20:38:35 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 03FBE6A071; Wed, 28 Jul 2021 20:38:34 +0000 (GMT) Received: from Bills-MacBook-Pro.local (unknown [9.211.91.192]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 28 Jul 2021 20:38:34 +0000 (GMT) Reply-To: wschmidt@linux.ibm.com Subject: Re: [PATCH 49/55] rs6000: Builtin expansion, part 6 To: will schmidt , gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org References: <743ac5ef9741fbd8028f5e78ecef1c6a55496181.1623941442.git.wschmidt@linux.ibm.com> From: Bill Schmidt Message-ID: Date: Wed, 28 Jul 2021 15:38:34 -0500 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.12.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-GB X-TM-AS-GCONF: 00 X-Proofpoint-GUID: g4_KQLabxQ0AgfyFFWs0gRua2JHJwMNY X-Proofpoint-ORIG-GUID: g4_KQLabxQ0AgfyFFWs0gRua2JHJwMNY X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-28_10:2021-07-27, 2021-07-28 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 spamscore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 phishscore=0 adultscore=0 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2107280113 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, NICE_REPLY_A, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Jul 2021 20:38:41 -0000 On 7/27/21 4:07 PM, will schmidt wrote: > On Thu, 2021-06-17 at 10:19 -0500, Bill Schmidt via Gcc-patches wrote: >> 2021-03-24 Bill Schmidt >> >> gcc/ >> * config/rs6000/rs6000-call.c (new_htm_spr_num): New function. >> (new_htm_expand_builtin): Implement. >> (rs6000_expand_new_builtin): Handle 32-bit and endian cases. >> --- >> gcc/config/rs6000/rs6000-call.c | 202 ++++++++++++++++++++++++++++++++ >> 1 file changed, 202 insertions(+) >> >> diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c >> index e1b685fb874..6b60f0852ef 100644 >> --- a/gcc/config/rs6000/rs6000-call.c >> +++ b/gcc/config/rs6000/rs6000-call.c >> @@ -15068,11 +15068,171 @@ new_mma_expand_builtin (tree exp, rtx target, insn_code icode, >> return target; >> } >> >> +/* Return the appropriate SPR number associated with the given builtin. */ >> +static inline HOST_WIDE_INT >> +new_htm_spr_num (enum rs6000_gen_builtins code) >> +{ >> + if (code == RS6000_BIF_GET_TFHAR >> + || code == RS6000_BIF_SET_TFHAR) >> + return TFHAR_SPR; >> + else if (code == RS6000_BIF_GET_TFIAR >> + || code == RS6000_BIF_SET_TFIAR) >> + return TFIAR_SPR; >> + else if (code == RS6000_BIF_GET_TEXASR >> + || code == RS6000_BIF_SET_TEXASR) >> + return TEXASR_SPR; >> + gcc_assert (code == RS6000_BIF_GET_TEXASRU >> + || code == RS6000_BIF_SET_TEXASRU); >> + return TEXASRU_SPR; >> +} > Ok, > > >> + >> /* Expand the HTM builtin in EXP and store the result in TARGET. */ >> static rtx >> new_htm_expand_builtin (bifdata *bifaddr, rs6000_gen_builtins fcode, >> tree exp, rtx target) >> { >> + tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); >> + bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node; >> + >> + if (!TARGET_POWERPC64 >> + && (fcode == RS6000_BIF_TABORTDC >> + || fcode == RS6000_BIF_TABORTDCI)) >> + { >> + error ("builtin %qs is only valid in 64-bit mode", bifaddr->bifname); >> + return const0_rtx; >> + } > ok > >> + >> + rtx op[MAX_HTM_OPERANDS], pat; >> + int nopnds = 0; >> + tree arg; >> + call_expr_arg_iterator iter; >> + insn_code icode = bifaddr->icode; >> + bool uses_spr = bif_is_htmspr (*bifaddr); >> + rtx cr = NULL_RTX; >> + >> + if (uses_spr) >> + icode = rs6000_htm_spr_icode (nonvoid); >> + const insn_operand_data *insn_op = &insn_data[icode].operand[0]; >> + >> + if (nonvoid) >> + { >> + machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode; >> + if (!target >> + || GET_MODE (target) != tmode >> + || (uses_spr && !(*insn_op->predicate) (target, tmode))) >> + target = gen_reg_rtx (tmode); >> + if (uses_spr) >> + op[nopnds++] = target; >> + } >> + >> + FOR_EACH_CALL_EXPR_ARG (arg, iter, exp) >> + { >> + if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS) >> + return const0_rtx; >> + >> + insn_op = &insn_data[icode].operand[nopnds]; >> + op[nopnds] = expand_normal (arg); >> + >> + if (!(*insn_op->predicate) (op[nopnds], insn_op->mode)) >> + { >> + if (!strcmp (insn_op->constraint, "n")) >> + { >> + int arg_num = (nonvoid) ? nopnds : nopnds + 1; >> + if (!CONST_INT_P (op[nopnds])) >> + error ("argument %d must be an unsigned literal", arg_num); >> + else >> + error ("argument %d is an unsigned literal that is " >> + "out of range", arg_num); >> + return const0_rtx; >> + } >> + op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]); >> + } >> + >> + nopnds++; >> + } >> + >> + /* Handle the builtins for extended mnemonics. These accept >> + no arguments, but map to builtins that take arguments. */ >> + switch (fcode) >> + { >> + case RS6000_BIF_TENDALL: /* Alias for: tend. 1 */ >> + case RS6000_BIF_TRESUME: /* Alias for: tsr. 1 */ >> + op[nopnds++] = GEN_INT (1); >> + break; >> + case RS6000_BIF_TSUSPEND: /* Alias for: tsr. 0 */ >> + op[nopnds++] = GEN_INT (0); >> + break; >> + default: >> + break; >> + } > ok > >> + >> + /* If this builtin accesses SPRs, then pass in the appropriate >> + SPR number and SPR regno as the last two operands. */ >> + if (uses_spr) >> + { >> + machine_mode mode = (TARGET_POWERPC64) ? DImode : SImode; >> + op[nopnds++] = gen_rtx_CONST_INT (mode, new_htm_spr_num (fcode)); >> + } >> + /* If this builtin accesses a CR, then pass in a scratch >> + CR as the last operand. */ >> + else if (bif_is_htmcr (*bifaddr)) > Given this is an if/else, presumably there are no builtins that use > both a SPR and access a CR ? Yes, that's right.  This is the same logic as used for HTM in the old builtins code. > >> + { >> + cr = gen_reg_rtx (CCmode); >> + op[nopnds++] = cr; >> + } >> + >> + switch (nopnds) >> + { >> + case 1: >> + pat = GEN_FCN (icode) (op[0]); >> + break; >> + case 2: >> + pat = GEN_FCN (icode) (op[0], op[1]); >> + break; >> + case 3: >> + pat = GEN_FCN (icode) (op[0], op[1], op[2]); >> + break; >> + case 4: >> + pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); >> + break; >> + default: >> + gcc_unreachable (); >> + } >> + if (!pat) >> + return NULL_RTX; >> + emit_insn (pat); > ok > >> + >> + if (bif_is_htmcr (*bifaddr)) >> + { >> + if (fcode == RS6000_BIF_TBEGIN) >> + { >> + /* Emit code to set TARGET to true or false depending on >> + whether the tbegin. instruction successfully or failed >> + to start a transaction. We do this by placing the 1's >> + complement of CR's EQ bit into TARGET. */ > s/successfully/succeeded/ ? Yes, blind copying was not a good strategy here.  I'll clean that up. Thanks for the review! Bill > > >> + rtx scratch = gen_reg_rtx (SImode); >> + emit_insn (gen_rtx_SET (scratch, >> + gen_rtx_EQ (SImode, cr, >> + const0_rtx))); >> + emit_insn (gen_rtx_SET (target, >> + gen_rtx_XOR (SImode, scratch, >> + GEN_INT (1)))); >> + } >> + else >> + { >> + /* Emit code to copy the 4-bit condition register field >> + CR into the least significant end of register TARGET. */ >> + rtx scratch1 = gen_reg_rtx (SImode); >> + rtx scratch2 = gen_reg_rtx (SImode); >> + rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0); >> + emit_insn (gen_movcc (subreg, cr)); >> + emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28))); >> + emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf))); >> + } >> + } >> + >> + if (nonvoid) >> + return target; > ok > >> return const0_rtx; >> } >> >> @@ -15316,6 +15476,48 @@ rs6000_expand_new_builtin (tree exp, rtx target, >> if (bif_is_htm (*bifaddr)) >> return new_htm_expand_builtin (bifaddr, fcode, exp, target); >> >> + if (bif_is_32bit (*bifaddr) && TARGET_32BIT) >> + { >> + if (fcode == RS6000_BIF_MFTB) >> + icode = CODE_FOR_rs6000_mftb_si; >> + else >> + gcc_unreachable (); >> + } > ok > >> + >> + if (bif_is_endian (*bifaddr) && BYTES_BIG_ENDIAN) >> + { >> + if (fcode == RS6000_BIF_LD_ELEMREV_V1TI) >> + icode = CODE_FOR_vsx_load_v1ti; >> + else if (fcode == RS6000_BIF_LD_ELEMREV_V2DF) >> + icode = CODE_FOR_vsx_load_v2df; >> + else if (fcode == RS6000_BIF_LD_ELEMREV_V2DI) >> + icode = CODE_FOR_vsx_load_v2di; >> + else if (fcode == RS6000_BIF_LD_ELEMREV_V4SF) >> + icode = CODE_FOR_vsx_load_v4sf; >> + else if (fcode == RS6000_BIF_LD_ELEMREV_V4SI) >> + icode = CODE_FOR_vsx_load_v4si; >> + else if (fcode == RS6000_BIF_LD_ELEMREV_V8HI) >> + icode = CODE_FOR_vsx_load_v8hi; >> + else if (fcode == RS6000_BIF_LD_ELEMREV_V16QI) >> + icode = CODE_FOR_vsx_load_v16qi; >> + else if (fcode == RS6000_BIF_ST_ELEMREV_V1TI) >> + icode = CODE_FOR_vsx_store_v1ti; >> + else if (fcode == RS6000_BIF_ST_ELEMREV_V2DF) >> + icode = CODE_FOR_vsx_store_v2df; >> + else if (fcode == RS6000_BIF_ST_ELEMREV_V2DI) >> + icode = CODE_FOR_vsx_store_v2di; >> + else if (fcode == RS6000_BIF_ST_ELEMREV_V4SF) >> + icode = CODE_FOR_vsx_store_v4sf; >> + else if (fcode == RS6000_BIF_ST_ELEMREV_V4SI) >> + icode = CODE_FOR_vsx_store_v4si; >> + else if (fcode == RS6000_BIF_ST_ELEMREV_V8HI) >> + icode = CODE_FOR_vsx_store_v8hi; >> + else if (fcode == RS6000_BIF_ST_ELEMREV_V16QI) >> + icode = CODE_FOR_vsx_store_v16qi; >> + else >> + gcc_unreachable (); > ok > lgtm, > thanks > -Will > >> + } >> + >> rtx pat; >> const int MAX_BUILTIN_ARGS = 6; >> tree arg[MAX_BUILTIN_ARGS];