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Subject: Re: [PATCH] Remove CC0
To: Eric Botcazou <botcazou@adacore.com>
Cc: Segher Boessenkool <segher@kernel.crashing.org>, gcc-patches@gcc.gnu.org
References: <952b5c888a98df98249088d81e954d64fad88827.1620082370.git.segher@kernel.crashing.org>
 <5e1b1ef9-dd0a-7dbe-458d-1df925bcecd1@foss.arm.com>
 <2091450.NgBsaNRSFp@fomalhaut>
From: Richard Earnshaw <Richard.Earnshaw@foss.arm.com>
Message-ID: <fb1a53c7-40b9-abfb-cc12-9962c8534b9f@foss.arm.com>
Date: Tue, 4 May 2021 17:24:15 +0100
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On 04/05/2021 17:22, Eric Botcazou wrote:
>> A quick look through the code suggests it's being used for thumb1 code
>> gen to try to reproduce the traditional CC0 type behaviour of
>> eliminating redundant compare operations when you have sequences such as
>>
>> cmp a, b
>> b<cond1> d1
>> cmp a, b
>> b<cond2> d2
>>
>> The second compare operation can be eliminated.
>>
>> It might be possible to eliminate this another way by reworking the
>> thumb1 codegen to expose the condition codes after register allocation
>> has completed (much like x86 does these days), but that would be quite a
>> lot of work right now.  I don't know if such splitting would directly
>> lead to the ability to remove the redundant compares - it might need a
>> new pass to spot them.
> 
> Do you mean in addition to the existing pass_compare_elim_after_reload?
> 

No, sounds like that would do the job.  :)

R.