From: Xi Ruoyao <xry111@xry111.site>
To: gcc-patches@gcc.gnu.org
Cc: Lulu Cheng <chenglulu@loongson.cn>,
Chenghua Xu <xuchenghua@loongson.cn>, Wang Xuerui <i@xen0n.name>
Subject: [PATCH 1/2] loongarch: add alternatives for idiv insns to improve code generation
Date: Thu, 07 Jul 2022 10:26:37 +0800 [thread overview]
Message-ID: <fb515535633d9d73e146f10e2639d15b1bd16541.camel@xry111.site> (raw)
In-Reply-To: <535ed6eaa19df38309a773f9bf2542c65f715b6b.camel@xry111.site>
Currently in the description of LoongArch integer division instructions,
the output is marked as earlyclobbered ('&'). It's necessary when
loongarch_check_zero_div_p() because clobbering operand 2 (divisor) will
make the checking for zero divisor impossible.
But, for -mno-check-zero-division (the default of GCC >= 12.2 for
optimized code), the output is not earlyclobbered at all. And, the
read of operand 1 only occurs before clobbering the output. So we make
three alternatives for an idiv instruction:
* (=r,r,r): For -mno-check-zero-division.
* (=&r,r,r): For -mcheck-zero-division.
* (=&r,0,r): For -mcheck-zero-division, to explicitly allow patterns
like "div.d $a0, $a0, $a1".
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_check_zero_div_p):
Remove static, for use in the machine description file.
* config/loongarch/loongarch-protos.h:
(loongarch_check_zero_div_p): Add prototype.
* config/loongarch/loongarch.md (enabled): New attr.
(*<optab><mode>3): Add (=r,r,r) and (=&r,0,r) alternatives for
idiv. Conditionally enable the alternatives using
loongarch_check_zero_div_p.
(<optab>di3_fake): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/div-1.c: New test.
* gcc.target/loongarch/div-2.c: New test.
* gcc.target/loongarch/div-3.c: New test.
---
gcc/config/loongarch/loongarch-protos.h | 1 +
gcc/config/loongarch/loongarch.cc | 2 +-
gcc/config/loongarch/loongarch.md | 28 +++++++++++++++-------
gcc/testsuite/gcc.target/loongarch/div-1.c | 9 +++++++
gcc/testsuite/gcc.target/loongarch/div-2.c | 9 +++++++
gcc/testsuite/gcc.target/loongarch/div-3.c | 9 +++++++
6 files changed, 49 insertions(+), 9 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/loongarch/div-1.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/div-2.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/div-3.c
diff --git a/gcc/config/loongarch/loongarch-protos.h b/gcc/config/loongarch/loongarch-protos.h
index 2144c2421ed..2287fd3763c 100644
--- a/gcc/config/loongarch/loongarch-protos.h
+++ b/gcc/config/loongarch/loongarch-protos.h
@@ -130,6 +130,7 @@ extern bool loongarch_symbol_binds_local_p (const_rtx);
extern const char *current_section_name (void);
extern unsigned int current_section_flags (void);
extern bool loongarch_use_ins_ext_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
+extern bool loongarch_check_zero_div_p (void);
union loongarch_gen_fn_ptrs
{
diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index d72b256df51..bc56282c9a7 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -2104,7 +2104,7 @@ loongarch_load_store_insns (rtx mem, rtx_insn *insn)
/* Return true if we need to trap on division by zero. */
-static bool
+bool
loongarch_check_zero_div_p (void)
{
/* if -m[no-]check-zero-division is given explicitly. */
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index d3c809e25f3..b002eb2ac22 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -110,6 +110,8 @@ (define_constants
;;
;; ....................
+(define_attr "enabled" "no,yes" (const_string "yes"))
+
(define_attr "got" "unset,load"
(const_string "unset"))
@@ -763,26 +765,36 @@ (define_expand "<optab><mode>3"
})
(define_insn "*<optab><mode>3"
- [(set (match_operand:GPR 0 "register_operand" "=&r")
- (any_div:GPR (match_operand:GPR 1 "register_operand" "r")
- (match_operand:GPR 2 "register_operand" "r")))]
+ [(set (match_operand:GPR 0 "register_operand" "=r,&r,&r")
+ (any_div:GPR (match_operand:GPR 1 "register_operand" "r,r,0")
+ (match_operand:GPR 2 "register_operand" "r,r,r")))]
""
{
return loongarch_output_division ("<insn>.<d><u>\t%0,%1,%2", operands);
}
[(set_attr "type" "idiv")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set (attr "enabled")
+ (if_then_else
+ (match_test "!!which_alternative == loongarch_check_zero_div_p()")
+ (const_string "yes")
+ (const_string "no")))])
(define_insn "<optab>di3_fake"
- [(set (match_operand:SI 0 "register_operand" "=&r")
- (any_div:SI (match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "register_operand" "r")))]
+ [(set (match_operand:SI 0 "register_operand" "=r,&r,&r")
+ (any_div:SI (match_operand:DI 1 "register_operand" "r,r,0")
+ (match_operand:DI 2 "register_operand" "r,r,r")))]
""
{
return loongarch_output_division ("<insn>.w<u>\t%0,%1,%2", operands);
}
[(set_attr "type" "idiv")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "SI")
+ (set (attr "enabled")
+ (if_then_else
+ (match_test "!!which_alternative == loongarch_check_zero_div_p()")
+ (const_string "yes")
+ (const_string "no")))])
;; Floating point multiply accumulate instructions.
diff --git a/gcc/testsuite/gcc.target/loongarch/div-1.c b/gcc/testsuite/gcc.target/loongarch/div-1.c
new file mode 100644
index 00000000000..b1683f8535f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/div-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcheck-zero-division" } */
+/* { dg-final { scan-assembler "div.\[wd\]\t\\\$r4,\\\$r4,\\\$r5" } } */
+
+long
+div(long a, long b)
+{
+ return a / b;
+}
diff --git a/gcc/testsuite/gcc.target/loongarch/div-2.c b/gcc/testsuite/gcc.target/loongarch/div-2.c
new file mode 100644
index 00000000000..4c2beb5b930
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/div-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mno-check-zero-division" } */
+/* { dg-final { scan-assembler "div.\[wd\]\t\\\$r4,\\\$r5,\\\$r4" } } */
+
+long
+div(long a, long b)
+{
+ return b / a;
+}
diff --git a/gcc/testsuite/gcc.target/loongarch/div-3.c b/gcc/testsuite/gcc.target/loongarch/div-3.c
new file mode 100644
index 00000000000..d25969263f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/div-3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcheck-zero-division" } */
+/* { dg-final { scan-assembler-not "div.\[wd\]\t\\\$r4,\\\$r5,\\\$r4" } } */
+
+long
+div(long a, long b)
+{
+ return b / a;
+}
--
2.37.0
next prev parent reply other threads:[~2022-07-07 2:26 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-07 2:23 [PATCH 0/2] loongarch: improve code generation for integer division Xi Ruoyao
2022-07-07 2:26 ` Xi Ruoyao [this message]
2022-07-07 2:29 ` [PATCH 2/2] loongarch: avoid unnecessary sign-extend after 32-bit division Xi Ruoyao
2022-07-08 1:23 ` [PATCH 0/2] loongarch: improve code generation for integer division Lulu Cheng
2022-07-10 2:20 ` Lulu Cheng
2022-07-10 3:44 ` Xi Ruoyao
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