From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 24380 invoked by alias); 23 Oct 2019 09:40:48 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 24372 invoked by uid 89); 23 Oct 2019 09:40:47 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-19.9 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 23 Oct 2019 09:40:46 +0000 Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x9N9b21o034488 for ; Wed, 23 Oct 2019 05:40:44 -0400 Received: from e06smtp03.uk.ibm.com (e06smtp03.uk.ibm.com [195.75.94.99]) by mx0a-001b2d01.pphosted.com with ESMTP id 2vtk21k6s9-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 23 Oct 2019 05:40:44 -0400 Received: from localhost by e06smtp03.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 23 Oct 2019 10:40:39 +0100 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x9N9ecUw58458344 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 23 Oct 2019 09:40:38 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 07E6811C050; Wed, 23 Oct 2019 09:40:38 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9AC6F11C052; Wed, 23 Oct 2019 09:40:36 +0000 (GMT) Received: from kewenlins-mbp.cn.ibm.com (unknown [9.200.147.149]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 23 Oct 2019 09:40:36 +0000 (GMT) Subject: [PATCH 2/3][rs6000] vector conversion RTL pattern update for same unit size From: "Kewen.Lin" To: GCC Patches Cc: Segher Boessenkool , Bill Schmidt References: <172addbc-3aae-084b-cce4-b9c8a194821d@linux.ibm.com> Date: Wed, 23 Oct 2019 09:42:00 -0000 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.14; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <172addbc-3aae-084b-cce4-b9c8a194821d@linux.ibm.com> Content-Type: multipart/mixed; boundary="------------1515363954B5D64C94FC7313" x-cbid: 19102309-0012-0000-0000-0000035BFF35 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19102309-0013-0000-0000-000021972D28 Message-Id: X-IsSubscribed: yes X-SW-Source: 2019-10/txt/msg01629.txt.bz2 This is a multi-part message in MIME format. --------------1515363954B5D64C94FC7313 Content-Type: text/plain; charset=gbk Content-Transfer-Encoding: 7bit Content-length: 620 Hi, For those fixed point <-> floating point vector conversion with same element unit size, such as: SP <-> SI, DP <-> DI, it's fine to use the existing RTL operations like any_fix/any_float for them. This patch is to update them with any_fix/any_float. Bootstrapped and regress tested on powerpc64le-linux-gnu. gcc/ChangeLog 2019-10-23 Kewen Lin * config/rs6000/vsx.md (UNSPEC_VSX_CV[SU]XWSP, UNSPEC_VSX_XVCV[SU]XDDP, UNSPEC_VSX_XVCVDP[SU]XDS, UNSPEC_VSX_XVCVSPSXWS): Remove. (vsx_xvcv[su]xddp, vsx_xvcvdp[su]xds, vsx_xvcvsp[su]xws, vsx_xvcv[su]xwsp): Update define_insn RTL patterns. --------------1515363954B5D64C94FC7313 Content-Type: text/plain; charset=UTF-8; x-mac-type="0"; x-mac-creator="0"; name="0002.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="0002.patch" Content-length: 5996 >From 39ae875d4ae6ce22e170aeb456ef307a1f5fd1e0 Mon Sep 17 00:00:00 2001 From: Kewen Lin Date: Wed, 23 Oct 2019 02:56:48 -0500 Subject: [PATCH 2/3] Update RTL pattern on vector SP<->[SU]W DP<->[SU]D conversion --- gcc/config/rs6000/vsx.md | 105 +++++++++++++---------------------------------- 1 file changed, 28 insertions(+), 77 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index d6f079c..83e4071 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -277,8 +277,6 @@ UNSPEC_VSX_CVUXDSP UNSPEC_VSX_CVSPSXDS UNSPEC_VSX_CVSPUXDS - UNSPEC_VSX_CVSXWSP - UNSPEC_VSX_CVUXWSP UNSPEC_VSX_FLOAT2 UNSPEC_VSX_UNS_FLOAT2 UNSPEC_VSX_FLOATE @@ -298,12 +296,7 @@ UNSPEC_VSX_DIVSD UNSPEC_VSX_DIVUD UNSPEC_VSX_MULSD - UNSPEC_VSX_XVCVSXDDP - UNSPEC_VSX_XVCVUXDDP - UNSPEC_VSX_XVCVDPSXDS - UNSPEC_VSX_XVCVDPUXDS UNSPEC_VSX_SIGN_EXTEND - UNSPEC_VSX_XVCVSPSXWS UNSPEC_VSX_XVCVSPSXDS UNSPEC_VSX_VSLO UNSPEC_VSX_EXTRACT @@ -2202,6 +2195,34 @@ ;; Convert and scale (used by vec_ctf, vec_cts, vec_ctu for double/long long) +(define_insn "vsx_xvcvxwsp" + [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") + (any_float:V4SF (match_operand:V4SI 1 "vsx_register_operand" "wa")))] + "VECTOR_UNIT_VSX_P (V4SFmode)" + "xvcvxwsp %x0,%x1" + [(set_attr "type" "vecfloat")]) + +(define_insn "vsx_xvcvxddp" + [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") + (any_float:V2DF (match_operand:V2DI 1 "vsx_register_operand" "wa")))] + "VECTOR_UNIT_VSX_P (V2DFmode)" + "xvcvxddp %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_insn "vsx_xvcvspxws" + [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa") + (any_fix:V4SI (match_operand:V4SF 1 "vsx_register_operand" "wa")))] + "VECTOR_UNIT_VSX_P (V4SFmode)" + "xvcvspxws %x0,%x1" + [(set_attr "type" "vecfloat")]) + +(define_insn "vsx_xvcvdpxds" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") + (any_fix:V2DI (match_operand:V2DF 1 "vsx_register_operand" "wa")))] + "VECTOR_UNIT_VSX_P (V2DFmode)" + "xvcvdpxds %x0,%x1" + [(set_attr "type" "vecdouble")]) + (define_expand "vsx_xvcvsxddp_scale" [(match_operand:V2DF 0 "vsx_register_operand") (match_operand:V2DI 1 "vsx_register_operand") @@ -2217,14 +2238,6 @@ DONE; }) -(define_insn "vsx_xvcvsxddp" - [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") - (unspec:V2DF [(match_operand:V2DI 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_XVCVSXDDP))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvsxddp %x0,%x1" - [(set_attr "type" "vecdouble")]) - (define_expand "vsx_xvcvuxddp_scale" [(match_operand:V2DF 0 "vsx_register_operand") (match_operand:V2DI 1 "vsx_register_operand") @@ -2240,14 +2253,6 @@ DONE; }) -(define_insn "vsx_xvcvuxddp" - [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") - (unspec:V2DF [(match_operand:V2DI 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_XVCVUXDDP))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvuxddp %x0,%x1" - [(set_attr "type" "vecdouble")]) - (define_expand "vsx_xvcvdpsxds_scale" [(match_operand:V2DI 0 "vsx_register_operand") (match_operand:V2DF 1 "vsx_register_operand") @@ -2270,26 +2275,6 @@ }) ;; convert vector of 64-bit floating point numbers to vector of -;; 64-bit signed integer -(define_insn "vsx_xvcvdpsxds" - [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") - (unspec:V2DI [(match_operand:V2DF 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_XVCVDPSXDS))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvdpsxds %x0,%x1" - [(set_attr "type" "vecdouble")]) - -;; convert vector of 32-bit floating point numbers to vector of -;; 32-bit signed integer -(define_insn "vsx_xvcvspsxws" - [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa") - (unspec:V4SI [(match_operand:V4SF 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_XVCVSPSXWS))] - "VECTOR_UNIT_VSX_P (V4SFmode)" - "xvcvspsxws %x0,%x1" - [(set_attr "type" "vecfloat")]) - -;; convert vector of 64-bit floating point numbers to vector of ;; 64-bit unsigned integer (define_expand "vsx_xvcvdpuxds_scale" [(match_operand:V2DI 0 "vsx_register_operand") @@ -2312,24 +2297,6 @@ DONE; }) -;; convert vector of 32-bit floating point numbers to vector of -;; 32-bit unsigned integer -(define_insn "vsx_xvcvspuxws" - [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa") - (unspec:V4SI [(match_operand:V4SF 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_XVCVSPSXWS))] - "VECTOR_UNIT_VSX_P (V4SFmode)" - "xvcvspuxws %x0,%x1" - [(set_attr "type" "vecfloat")]) - -(define_insn "vsx_xvcvdpuxds" - [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") - (unspec:V2DI [(match_operand:V2DF 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_XVCVDPUXDS))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvdpuxds %x0,%x1" - [(set_attr "type" "vecdouble")]) - ;; Convert from 64-bit to 32-bit types ;; Note, favor the Altivec registers since the usual use of these instructions ;; is in vector converts and we need to use the Altivec vperm instruction. @@ -2416,22 +2383,6 @@ "xvcvspuxds %x0,%x1" [(set_attr "type" "vecdouble")]) -(define_insn "vsx_xvcvsxwsp" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:V4SI 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVSXWSP))] - "VECTOR_UNIT_VSX_P (V4SFmode)" - "xvcvsxwsp %x0,%x1" - [(set_attr "type" "vecfloat")]) - -(define_insn "vsx_xvcvuxwsp" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF[(match_operand:V4SI 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVUXWSP))] - "VECTOR_UNIT_VSX_P (V4SFmode)" - "xvcvuxwsp %x0,%x1" - [(set_attr "type" "vecfloat")]) - ;; Generate float2 double ;; convert two double to float (define_expand "float2_v2df" -- 2.7.4 --------------1515363954B5D64C94FC7313--