* [PATCH v1] RISC-V: Use FRM_DYN when add the rounding mode operand
@ 2023-07-04 12:26 pan2.li
2023-07-04 12:54 ` Robin Dapp
2023-07-05 2:07 ` juzhe.zhong
0 siblings, 2 replies; 5+ messages in thread
From: pan2.li @ 2023-07-04 12:26 UTC (permalink / raw)
To: gcc-patches
Cc: juzhe.zhong, rdapp.gcc, jeffreyalaw, pan2.li, yanzhang.wang, kito.cheng
From: Pan Li <pan2.li@intel.com>
This patch would like to take FRM_DYN const rtx as the rounding mode
operand according to the RVV spec, which takes the dyn as the only
rounding mode for floating-point.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_exact_insn): Use FRM_DYN instead of const0.
---
gcc/config/riscv/riscv-vector-builtins.cc | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 648c765a5d1..3a53b56effa 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3569,11 +3569,10 @@ function_expander::use_exact_insn (insn_code icode)
if (base->has_rounding_mode_operand_p ())
add_input_operand (call_expr_nargs (exp) - 2);
- /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
- We add default rounding mode for the intrinsics that didn't model rounding
- mode yet. */
+ /* The RVV floating-point only support dynamic rounding mode in the
+ FRM register. */
if (opno != insn_data[icode].n_generator_args)
- add_input_operand (Pmode, const0_rtx);
+ add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode));
return generate_insn (icode);
}
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v1] RISC-V: Use FRM_DYN when add the rounding mode operand
2023-07-04 12:26 [PATCH v1] RISC-V: Use FRM_DYN when add the rounding mode operand pan2.li
@ 2023-07-04 12:54 ` Robin Dapp
2023-07-05 2:07 ` juzhe.zhong
1 sibling, 0 replies; 5+ messages in thread
From: Robin Dapp @ 2023-07-04 12:54 UTC (permalink / raw)
To: pan2.li, gcc-patches
Cc: rdapp.gcc, juzhe.zhong, jeffreyalaw, yanzhang.wang, kito.cheng
Hi Pan,
in general this looks good to me. I would have expected the
change in the other patch I just looked at though ;) Sure
it's intrinsics this time but the same principle.
Regards
Robin
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v1] RISC-V: Use FRM_DYN when add the rounding mode operand
2023-07-04 12:26 [PATCH v1] RISC-V: Use FRM_DYN when add the rounding mode operand pan2.li
2023-07-04 12:54 ` Robin Dapp
@ 2023-07-05 2:07 ` juzhe.zhong
2023-07-05 7:16 ` Kito Cheng
1 sibling, 1 reply; 5+ messages in thread
From: juzhe.zhong @ 2023-07-05 2:07 UTC (permalink / raw)
To: pan2.li, gcc-patches
Cc: Robin Dapp, jeffreyalaw, pan2.li, yanzhang.wang, kito.cheng
[-- Attachment #1: Type: text/plain, Size: 1673 bytes --]
LGTM.
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2023-07-04 20:26
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Use FRM_DYN when add the rounding mode operand
From: Pan Li <pan2.li@intel.com>
This patch would like to take FRM_DYN const rtx as the rounding mode
operand according to the RVV spec, which takes the dyn as the only
rounding mode for floating-point.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_exact_insn): Use FRM_DYN instead of const0.
---
gcc/config/riscv/riscv-vector-builtins.cc | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 648c765a5d1..3a53b56effa 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3569,11 +3569,10 @@ function_expander::use_exact_insn (insn_code icode)
if (base->has_rounding_mode_operand_p ())
add_input_operand (call_expr_nargs (exp) - 2);
- /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
- We add default rounding mode for the intrinsics that didn't model rounding
- mode yet. */
+ /* The RVV floating-point only support dynamic rounding mode in the
+ FRM register. */
if (opno != insn_data[icode].n_generator_args)
- add_input_operand (Pmode, const0_rtx);
+ add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode));
return generate_insn (icode);
}
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v1] RISC-V: Use FRM_DYN when add the rounding mode operand
2023-07-05 2:07 ` juzhe.zhong
@ 2023-07-05 7:16 ` Kito Cheng
2023-07-05 14:27 ` Li, Pan2
0 siblings, 1 reply; 5+ messages in thread
From: Kito Cheng @ 2023-07-05 7:16 UTC (permalink / raw)
To: juzhe.zhong; +Cc: pan2.li, gcc-patches, Robin Dapp, jeffreyalaw, yanzhang.wang
LGTM
On Wed, Jul 5, 2023 at 10:08 AM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> LGTM.
>
>
>
> juzhe.zhong@rivai.ai
>
> From: pan2.li
> Date: 2023-07-04 20:26
> To: gcc-patches
> CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
> Subject: [PATCH v1] RISC-V: Use FRM_DYN when add the rounding mode operand
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to take FRM_DYN const rtx as the rounding mode
> operand according to the RVV spec, which takes the dyn as the only
> rounding mode for floating-point.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins.cc
> (function_expander::use_exact_insn): Use FRM_DYN instead of const0.
> ---
> gcc/config/riscv/riscv-vector-builtins.cc | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
> index 648c765a5d1..3a53b56effa 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -3569,11 +3569,10 @@ function_expander::use_exact_insn (insn_code icode)
> if (base->has_rounding_mode_operand_p ())
> add_input_operand (call_expr_nargs (exp) - 2);
> - /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
> - We add default rounding mode for the intrinsics that didn't model rounding
> - mode yet. */
> + /* The RVV floating-point only support dynamic rounding mode in the
> + FRM register. */
> if (opno != insn_data[icode].n_generator_args)
> - add_input_operand (Pmode, const0_rtx);
> + add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode));
> return generate_insn (icode);
> }
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH v1] RISC-V: Use FRM_DYN when add the rounding mode operand
2023-07-05 7:16 ` Kito Cheng
@ 2023-07-05 14:27 ` Li, Pan2
0 siblings, 0 replies; 5+ messages in thread
From: Li, Pan2 @ 2023-07-05 14:27 UTC (permalink / raw)
To: Kito Cheng, juzhe.zhong
Cc: gcc-patches, Robin Dapp, jeffreyalaw, Wang, Yanzhang
Committed, thanks Juzhe and Kito.
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Wednesday, July 5, 2023 3:16 PM
To: juzhe.zhong@rivai.ai
Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>; Robin Dapp <rdapp.gcc@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v1] RISC-V: Use FRM_DYN when add the rounding mode operand
LGTM
On Wed, Jul 5, 2023 at 10:08 AM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> LGTM.
>
>
>
> juzhe.zhong@rivai.ai
>
> From: pan2.li
> Date: 2023-07-04 20:26
> To: gcc-patches
> CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
> Subject: [PATCH v1] RISC-V: Use FRM_DYN when add the rounding mode operand
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to take FRM_DYN const rtx as the rounding mode
> operand according to the RVV spec, which takes the dyn as the only
> rounding mode for floating-point.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins.cc
> (function_expander::use_exact_insn): Use FRM_DYN instead of const0.
> ---
> gcc/config/riscv/riscv-vector-builtins.cc | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
> index 648c765a5d1..3a53b56effa 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -3569,11 +3569,10 @@ function_expander::use_exact_insn (insn_code icode)
> if (base->has_rounding_mode_operand_p ())
> add_input_operand (call_expr_nargs (exp) - 2);
> - /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.
> - We add default rounding mode for the intrinsics that didn't model rounding
> - mode yet. */
> + /* The RVV floating-point only support dynamic rounding mode in the
> + FRM register. */
> if (opno != insn_data[icode].n_generator_args)
> - add_input_operand (Pmode, const0_rtx);
> + add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode));
> return generate_insn (icode);
> }
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-07-05 14:27 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2023-07-04 12:26 [PATCH v1] RISC-V: Use FRM_DYN when add the rounding mode operand pan2.li
2023-07-04 12:54 ` Robin Dapp
2023-07-05 2:07 ` juzhe.zhong
2023-07-05 7:16 ` Kito Cheng
2023-07-05 14:27 ` Li, Pan2
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