From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 1EEAC3860757 for ; Thu, 20 Oct 2022 09:27:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 1EEAC3860757 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29K9CgjC022964; Thu, 20 Oct 2022 09:27:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=message-id : date : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding : mime-version; s=pp1; bh=NNgGcRG+Q/wCY/hYKXszU1yeM+LLcHa4Es/r5iSKuHk=; b=iv7OL0ooGpQGjx8YaUCiGKdaBHXQdvSH7v409Y0Wn1aSV6XObM84Y8lnkEuYg5fu69TW maWFIXyJrus/uCo9f3izTSYJplvdyqgjhmpDVF3lf/usq9X4EYkyHsuAZp6Sb2jKb8tL 9M+QYpimO48G1HS2DvGk+Q4KglRDNopDPdWbAecQcQj8tR0mPDJWvt3qPhWw1l7Y5QFQ aR/FjN7y0lD7djW2/PPAzZb/q36uYQopCgblCCWmojB2gr0TWieh69Ruikf0qZnKLfxy 0ctPeHAla8Cj7yw7bINzOv3A8aqYHeto3cHQJuEgLnfxe6zvxMlfS92Quiyp1C+CdVtd vA== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3kb3g7rddg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 20 Oct 2022 09:27:49 +0000 Received: from m0098404.ppops.net (m0098404.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 29K9EHDv000353; Thu, 20 Oct 2022 09:27:49 GMT Received: from ppma01fra.de.ibm.com (46.49.7a9f.ip4.static.sl-reverse.com [159.122.73.70]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3kb3g7rdcr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 20 Oct 2022 09:27:49 +0000 Received: from pps.filterd (ppma01fra.de.ibm.com [127.0.0.1]) by ppma01fra.de.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 29K9MjID009973; Thu, 20 Oct 2022 09:27:47 GMT Received: from b06cxnps3074.portsmouth.uk.ibm.com (d06relay09.portsmouth.uk.ibm.com [9.149.109.194]) by ppma01fra.de.ibm.com with ESMTP id 3k99fn40g0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 20 Oct 2022 09:27:46 +0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 29K9Rhgo6226610 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 20 Oct 2022 09:27:43 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6B3F44C052; Thu, 20 Oct 2022 09:27:43 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8FF6F4C044; Thu, 20 Oct 2022 09:27:41 +0000 (GMT) Received: from [9.197.227.147] (unknown [9.197.227.147]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 20 Oct 2022 09:27:41 +0000 (GMT) Message-ID: Date: Thu, 20 Oct 2022 17:27:39 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCH v3, rs6000] Change mode and insn condition for VSX scalar extract/insert instructions Content-Language: en-US To: HAO CHEN GUI Cc: Segher Boessenkool , David , Peter Bergner , gcc-patches References: <5a2217c9-784a-d180-fabd-45e5ea88db9f@linux.ibm.com> From: "Kewen.Lin" In-Reply-To: <5a2217c9-784a-d180-fabd-45e5ea88db9f@linux.ibm.com> Content-Type: text/plain; charset=UTF-8 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: RWSXgeBWijvF1WUBhHfHRNOWYlVCIkPQ X-Proofpoint-GUID: CCgIuMiZBLEfrFVF8Fpn30S0JMoFhcPi Content-Transfer-Encoding: 7bit X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-20_02,2022-10-19_04,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 mlxlogscore=999 lowpriorityscore=0 impostorscore=0 suspectscore=0 bulkscore=0 mlxscore=0 malwarescore=0 spamscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210200053 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,NICE_REPLY_A,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Haochen, Sorry for late review, some comments are inline. on 2022/9/7 15:44, HAO CHEN GUI wrote: > Hi, > > For scalar extract/insert instructions, exponent field can be stored in a > 32-bit register. So this patch changes the mode of exponent field from DI to > SI. The instructions using DI registers can be invoked with -mpowerpc64 in a > 32-bit environment. The patch changes insn condition from TARGET_64BIT to > TARGET_POWERPC64 for those instructions. > > This patch also changes prototypes of relevant built-ins and effective > target of test cases. > > Bootstrapped and tested on powerpc64-linux BE and LE with no regressions. > Is this okay for trunk? Any recommendations? Thanks a lot. > > ChangeLog > 2022-09-07 Haochen Gui > > gcc/ > * config/rs6000/rs6000-builtins.def > (__builtin_vsx_scalar_extract_exp): Set return type to const unsigned > int. > (__builtin_vsx_scalar_extract_sig): Set return type to const unsigned > long long. > (__builtin_vsx_scalar_insert_exp): Set type of second argument to > unsigned int. > (__builtin_vsx_scalar_insert_exp_dp): Likewise. > * config/rs6000/vsx.md (xsxexpdp): Set mode of first operand to > SImode. Remove TARGET_64BIT from insn condition. > (xsxsigdp): Change insn condition from TARGET_64BIT to TARGET_POWERPC64. > (xsiexpdp): Change insn condition from TARGET_64BIT to > TARGET_POWERPC64. Set mode of third operand to SImode. > (xsiexpdpf): Set mode of third operand to SImode. Remove TARGET_64BIT > from insn condition. > > gcc/testsuite/ > * gcc.target/powerpc/bfp/scalar-extract-exp-0.c: Change effective > target from lp64 to has_arch_ppc64. > * gcc.target/powerpc/bfp/scalar-extract-exp-6.c: Likewise. > * gcc.target/powerpc/bfp/scalar-extract-sig-0.c: Likewise. > * gcc.target/powerpc/bfp/scalar-extract-sig-6.c: Likewise. > * gcc.target/powerpc/bfp/scalar-insert-exp-0.c: Likewise. > * gcc.target/powerpc/bfp/scalar-insert-exp-12.c: Likewise. > * gcc.target/powerpc/bfp/scalar-insert-exp-13.c: Likewise. > * gcc.target/powerpc/bfp/scalar-insert-exp-3.c: Likewise. > > patch.diff > diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def > index f76f54793d7..ca2a1d7657e 100644 > --- a/gcc/config/rs6000/rs6000-builtins.def > +++ b/gcc/config/rs6000/rs6000-builtins.def > @@ -2847,17 +2847,17 @@ > pure vsc __builtin_vsx_lxvl (const void *, signed long); > LXVL lxvl {} > > - const signed long __builtin_vsx_scalar_extract_exp (double); > + const unsigned int __builtin_vsx_scalar_extract_exp (double); > VSEEDP xsxexpdp {} > With the relevant define_insn condition change and this prototype change, I think this bif can work on 32 bit environment. So it should be moved to section [power9] instead of [power9-64]? If we want this supported on 32 bit, the related documentation and test cases need some updates accordingly. For the documentation, such as "The *scalar_extract_exp* and scalar_extract_sig functions require *a 64-bit environment* supporting ISA 3.0 ...." in [1]. For the test case, please see separated comments in test case part below. [1] https://gcc.gnu.org/onlinedocs//gcc/PowerPC-AltiVec-Built-in-Functions-Available-on-ISA-3_002e0.html The above comments are also applied for the bif __builtin_vsx_scalar_insert_exp_dp. > - const signed long __builtin_vsx_scalar_extract_sig (double); > + const unsigned long long __builtin_vsx_scalar_extract_sig (double); > VSESDP xsxsigdp {} > > const double __builtin_vsx_scalar_insert_exp (unsigned long long, \ > - unsigned long long); > + unsigned int); > VSIEDP xsiexpdp {} > > - const double __builtin_vsx_scalar_insert_exp_dp (double, unsigned long long); > + const double __builtin_vsx_scalar_insert_exp_dp (double, unsigned int); > VSIEDPF xsiexpdpf {} > > pure vsc __builtin_vsx_xl_len_r (void *, signed long); > diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md > index e226a93bbe5..9d3a2340a79 100644 > --- a/gcc/config/rs6000/vsx.md > +++ b/gcc/config/rs6000/vsx.md > @@ -5095,10 +5095,10 @@ (define_insn "xsxexpqp_" > > ;; VSX Scalar Extract Exponent Double-Precision > (define_insn "xsxexpdp" > - [(set (match_operand:DI 0 "register_operand" "=r") > - (unspec:DI [(match_operand:DF 1 "vsx_register_operand" "wa")] > + [(set (match_operand:SI 0 "register_operand" "=r") > + (unspec:SI [(match_operand:DF 1 "vsx_register_operand" "wa")] > UNSPEC_VSX_SXEXPDP))] > - "TARGET_P9_VECTOR && TARGET_64BIT" > + "TARGET_P9_VECTOR" > "xsxexpdp %0,%x1" > [(set_attr "type" "integer")]) > > @@ -5116,7 +5116,7 @@ (define_insn "xsxsigdp" > [(set (match_operand:DI 0 "register_operand" "=r") > (unspec:DI [(match_operand:DF 1 "vsx_register_operand" "wa")] > UNSPEC_VSX_SXSIG))] > - "TARGET_P9_VECTOR && TARGET_64BIT" > + "TARGET_P9_VECTOR && TARGET_POWERPC64" > "xsxsigdp %0,%x1" > [(set_attr "type" "integer")]) > > @@ -5145,9 +5145,9 @@ (define_insn "xsiexpqp_" > (define_insn "xsiexpdp" > [(set (match_operand:DF 0 "vsx_register_operand" "=wa") > (unspec:DF [(match_operand:DI 1 "register_operand" "r") > - (match_operand:DI 2 "register_operand" "r")] > + (match_operand:SI 2 "register_operand" "r")] > UNSPEC_VSX_SIEXPDP))] > - "TARGET_P9_VECTOR && TARGET_64BIT" > + "TARGET_P9_VECTOR && TARGET_POWERPC64" > "xsiexpdp %x0,%1,%2" > [(set_attr "type" "fpsimple")]) > > @@ -5155,9 +5155,9 @@ (define_insn "xsiexpdp" > (define_insn "xsiexpdpf" > [(set (match_operand:DF 0 "vsx_register_operand" "=wa") > (unspec:DF [(match_operand:DF 1 "register_operand" "r") > - (match_operand:DI 2 "register_operand" "r")] > + (match_operand:SI 2 "register_operand" "r")] > UNSPEC_VSX_SIEXPDP))] > - "TARGET_P9_VECTOR && TARGET_64BIT" > + "TARGET_P9_VECTOR" > "xsiexpdp %x0,%1,%2" > [(set_attr "type" "fpsimple")]) > > diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c > index 35bf1b240f3..9f327a4be6c 100644 > --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c > +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c > @@ -1,7 +1,7 @@ > -/* { dg-do compile { target { powerpc*-*-* } } } */ > -/* { dg-require-effective-target lp64 } */ > -/* { dg-require-effective-target powerpc_p9vector_ok } */ > +/* { dg-do compile } */ > /* { dg-options "-mdejagnu-cpu=power9" } */ > +/* { dg-require-effective-target has_arch_ppc64 } */ > +/* { dg-require-effective-target powerpc_p9vector_ok } */ If we all agree bif scalar_extract_exp should work on 32 bit w/i or w/o has_arch_ppc64 support, then we should remove the has_arch_ppc64 check here. > > /* This test should succeed only on 64-bit configurations. */ This comment should be updated as well. Same for scalar-extract-exp-6.c. Besides, scalar-extract-exp-1.c doesn't need lp64; scalar-extract-exp-2.c isn't effective any more. And similar for scalar-insert-exp-{3,4,5}.c and scalar-insert-exp-13.c. BR, Kewen > #include > diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c > index b9dd7d61aae..136471a35b3 100644 > --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c > +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c > @@ -1,7 +1,7 @@ > -/* { dg-do run { target { powerpc*-*-* } } } */ > -/* { dg-require-effective-target lp64 } */ > -/* { dg-require-effective-target p9vector_hw } */ > +/* { dg-do run } */ > /* { dg-options "-mdejagnu-cpu=power9" } */ > +/* { dg-require-effective-target has_arch_ppc64 } */ > +/* { dg-require-effective-target p9vector_hw } */ > > /* This test should succeed only on 64-bit configurations. */ > #include > diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c > index 637080652b7..3be7eb13566 100644 > --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c > +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c > @@ -1,7 +1,7 @@ > -/* { dg-do compile { target { powerpc*-*-* } } } */ > -/* { dg-require-effective-target lp64 } */ > -/* { dg-require-effective-target powerpc_p9vector_ok } */ > +/* { dg-do compile } */ > /* { dg-options "-mdejagnu-cpu=power9" } */ > +/* { dg-require-effective-target has_arch_ppc64 } */ > +/* { dg-require-effective-target powerpc_p9vector_ok } */ > > /* This test should succeed only on 64-bit configurations. */ > #include > diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c > index c85072da138..b96a745157d 100644 > --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c > +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c > @@ -1,7 +1,7 @@ > -/* { dg-do run { target { powerpc*-*-* } } } */ > -/* { dg-require-effective-target lp64 } */ > -/* { dg-require-effective-target p9vector_hw } */ > +/* { dg-do run } */ > /* { dg-options "-mdejagnu-cpu=power9" } */ > +/* { dg-require-effective-target has_arch_ppc64 } */ > +/* { dg-require-effective-target p9vector_hw } */ > > /* This test should succeed only on 64-bit configurations. */ > #include > diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c > index d8243258a67..074c23f4530 100644 > --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c > +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c > @@ -1,7 +1,7 @@ > -/* { dg-do compile { target { powerpc*-*-* } } } */ > -/* { dg-require-effective-target lp64 } */ > -/* { dg-require-effective-target powerpc_p9vector_ok } */ > +/* { dg-do compile } */ > /* { dg-options "-mdejagnu-cpu=power9" } */ > +/* { dg-require-effective-target has_arch_ppc64 } */ > +/* { dg-require-effective-target powerpc_p9vector_ok } */ > > /* This test should succeed only on 64-bit configurations. */ > #include > diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c > index 384fc9cc675..6260e577c7d 100644 > --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c > +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c > @@ -1,7 +1,7 @@ > -/* { dg-do run { target { powerpc*-*-* } } } */ > -/* { dg-require-effective-target lp64 } */ > -/* { dg-require-effective-target p9vector_hw } */ > +/* { dg-do run } */ > /* { dg-options "-mdejagnu-cpu=power9" } */ > +/* { dg-require-effective-target has_arch_ppc64 } */ > +/* { dg-require-effective-target p9vector_hw } */ > > /* This test should succeed only on 64-bit configurations. */ > #include > diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c > index 0e004224277..f024d390a5d 100644 > --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c > +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c > @@ -1,7 +1,7 @@ > -/* { dg-do run { target { powerpc*-*-* } } } */ > -/* { dg-require-effective-target lp64 } */ > -/* { dg-require-effective-target p9vector_hw } */ > +/* { dg-do run } */ > /* { dg-options "-mdejagnu-cpu=power9" } */ > +/* { dg-require-effective-target has_arch_ppc64 } */> +/* { dg-require-effective-target p9vector_hw } */ > > /* This test should succeed only on 64-bit configurations. */ > #include > diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c > index 3ecbe3318e8..a65dce901df 100644 > --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c > +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c > @@ -1,7 +1,7 @@ > -/* { dg-do compile { target { powerpc*-*-* } } } */ > -/* { dg-require-effective-target lp64 } */ > -/* { dg-require-effective-target powerpc_p9vector_ok } */ > +/* { dg-do compile } */ > /* { dg-options "-mdejagnu-cpu=power9" } */ > +/* { dg-require-effective-target has_arch_ppc64 } */ > +/* { dg-require-effective-target powerpc_p9vector_ok } */ > > /* This test should succeed only on 64-bit configurations. */ > #include