Re: [PATCH] RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert

[Jeff Law <jeffreyalaw@gmail.com>]

On 9/11/23 20:33, Lehua Ding wrote:
> Hi Edwin,
> 
> Sorry to bother you. I have a small question for you.
> 
> On 2023/9/12 6:52, Edwin Lu wrote:
>> --- a/gcc/config/riscv/autovec-opt.md +++ 
>> b/gcc/config/riscv/autovec-opt.md @@ -649,7 +649,8 @@ 
>> (define_insn_and_split "*cond_<optab><mode>" gen_int_mode 
>> (GET_MODE_NUNITS (<MODE>mode), Pmode)}; 
>> riscv_vector::expand_cond_len_unop (icode, ops); DONE; -}) +} 
>> +[(set_attr "type" "vector")])
> 
> Is it necessary to add type attribute to these INSNs that exist only 
> before split1 pass? These instructions are expanded into the pattern in 
> vector.md after split1 pass and do not reach the sched1 pass at all. If 
> so, I feel that these patterns cannot be added, and it is reasonable to 
> report an error if these INSNs reach sched1 pass. Thanks.
I'd rather be consistent and make it policy that every insn has a type.

The next thing I'd like to do (and it's probably much more work) is to 
validate that every insn type maps to a functional unit for the sched2 
pass.  The scheduler will do some horrible things to the generated code 
when lots of insns either don't have types or the types aren't matched 
to a functional unit.

Jeff