From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 9FD7B3858408 for ; Sat, 12 Nov 2022 06:52:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9FD7B3858408 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.20.4.52]) by gateway (Coremail) with SMTP id _____8DxTtusQm9jkFwGAA--.19845S3; Sat, 12 Nov 2022 14:52:28 +0800 (CST) Received: from [10.20.4.52] (unknown [10.20.4.52]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Cxb+KrQm9jJVMRAA--.47465S2; Sat, 12 Nov 2022 14:52:27 +0800 (CST) Subject: Re: [PATCH v2 3/4] LoongArch: Add fscaleb.{s,d} instructions as ldexp{sf,df}3 To: Xi Ruoyao , gcc-patches@gcc.gnu.org Cc: Wang Xuerui , Chenghua Xu , Xiaolin Tang References: <20221109135329.952128-1-xry111@xry111.site> <20221109135329.952128-4-xry111@xry111.site> From: Lulu Cheng Message-ID: Date: Sat, 12 Nov 2022 14:52:26 +0800 User-Agent: Mozilla/5.0 (X11; Linux mips64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-CM-TRANSID:AQAAf8Cxb+KrQm9jJVMRAA--.47465S2 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBjvJXoW3XF1rAw4DuFyfur4rur4fuFg_yoW7uw4Dpr s7AFyUtFW8Xr1kJwnFg3W5JFyYqr18Jw1UZr13GFy8ArsFvFnFqr1jgr1qgF4UCw4kJr4I vF45Z343uFy3JrDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU bxkYFVCjjxCrM7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s 1l1IIY67AEw4v_Jr0_Jr4l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVWUJVWUCwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwA2z4 x0Y4vEx4A2jsIE14v26r4j6F4UM28EF7xvwVC2z280aVCY1x0267AKxVW8JVW8Jr1le2I2 62IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27wAqx4xG64xvF2IEw4 CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r4j6F4UMcvj eVCFs4IE7xkEbVWUJVW8JwACjcxG0xvEwIxGrwCYjI0SjxkI62AI1cAE67vIY487MxAIw2 8IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4l x2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrw CI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI 42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z2 80aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU8oGQDUUUUU== X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00,BODY_8BITS,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_NUMSUBJECT,KAM_SHORT,NICE_REPLY_A,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: 在 2022/11/12 下午12:40, Xi Ruoyao 写道: > On Sat, 2022-11-12 at 11:54 +0800, Lulu Cheng wrote: >> 在 2022/11/9 下午9:53, Xi Ruoyao 写道: >>> This allows optimizing __builtin_ldexp{,f} and __builtin_scalbn{,f} >>> with >>> -fno-math-errno. >>> >>> IMODE is added because we can't hard code SI for operand 2: >>> fscaleb.d >>> instruction always take the high half of both source registers into >>> account.  See my_ldexp_long in the test case. >>> >>> gcc/ChangeLog: >>> >>>         * config/loongarch/loongarch.md (UNSPEC_FSCALEB): New >>> unspec. >>>         (type): Add fscaleb. >>>         (IMODE): New mode attr. >>>         (ldexp3): New instruction template. >>> >>> gcc/testsuite/ChangeLog: >>> >>>         * gcc.target/loongarch/fscaleb.c: New test. >>> --- >>>   gcc/config/loongarch/loongarch.md            | 26 ++++++++++- >>>   gcc/testsuite/gcc.target/loongarch/fscaleb.c | 48 >>> ++++++++++++++++++++ >>>   2 files changed, 72 insertions(+), 2 deletions(-) >>>   create mode 100644 gcc/testsuite/gcc.target/loongarch/fscaleb.c >>> >>> diff --git a/gcc/config/loongarch/loongarch.md >>> b/gcc/config/loongarch/loongarch.md >>> index eb127c346a3..c141c9adde2 100644 >>> --- a/gcc/config/loongarch/loongarch.md >>> +++ b/gcc/config/loongarch/loongarch.md >>> @@ -41,6 +41,7 @@ (define_c_enum "unspec" [ >>>     UNSPEC_FTINT >>>     UNSPEC_FTINTRM >>>     UNSPEC_FTINTRP >>> +  UNSPEC_FSCALEB >>> >>>     ;; Override return address for exception handling. >>>     UNSPEC_EH_RETURN >>> @@ -220,6 +221,7 @@ (define_attr "qword_mode" "no,yes" >>>   ;; fcmp               floating point compare >>>   ;; fcopysign  floating point copysign >>>   ;; fcvt               floating point convert >>> +;; fscaleb     floating point scale >>>   ;; fsqrt      floating point square root >>>   ;; frsqrt       floating point reciprocal square root >>>   ;; multi      multiword sequence (or user asm statements) >>> @@ -231,8 +233,8 @@ (define_attr "type" >>> >>> "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxs >>> tore, >>>      prefetch,prefetchx,condmove,mgtf,mftg,const,arith,logical, >>>      shift,slt,signext,clz,trap,imul,idiv,move, >>> - >>> fmove,fadd,fmul,fmadd,fdiv,frdiv,fabs,fneg,fcmp,fcopysign,fcvt,fsqrt >>> , >>> -   frsqrt,accext,accmod,multi,atomic,syncloop,nop,ghost" >>> + >>> fmove,fadd,fmul,fmadd,fdiv,frdiv,fabs,fneg,fcmp,fcopysign,fcvt,fscal >>> eb, >>> +   fsqrt,frsqrt,accext,accmod,multi,atomic,syncloop,nop,ghost" >>>     (cond [(eq_attr "jirl" "!unset") (const_string "call") >>>          (eq_attr "got" "load") (const_string "load") >>> >>> @@ -418,6 +420,10 @@ (define_mode_attr UNITMODE [(SF "SF") (DF >>> "DF")]) >>>   ;; the controlling mode. >>>   (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (TF "DI")]) >>> >>> +;; This attribute gives the integer mode that has the same size of >>> a >>> +;; floating-point mode. >>> +(define_mode_attr IMODE [(SF "SI") (DF "DI")]) >>> + >>>   ;; This code iterator allows signed and unsigned widening >>> multiplications >>>   ;; to use the same template. >>>   (define_code_iterator any_extend [sign_extend zero_extend]) >>> @@ -1014,7 +1020,23 @@ (define_insn "copysign3" >>>     "fcopysign.\t%0,%1,%2" >>>     [(set_attr "type" "fcopysign") >>>      (set_attr "mode" "")]) >>> + >>> +;; >>> +;;  .................... >>> +;; >>> +;;     FLOATING POINT SCALE >>> +;; >>> +;;  .................... >>> >>> +(define_insn "ldexp3" >>> +  [(set (match_operand:ANYF 0 "register_operand" "=f") >>> +       (unspec:ANYF [(match_operand:ANYF    1 "register_operand" >>> "f") >>> +                     (match_operand: 2 "register_operand" >>> "f")] >>> +                    UNSPEC_FSCALEB))] >>> +  "TARGET_HARD_FLOAT" >>> +  "fscaleb.\t%0,%1,%2" >>> +  [(set_attr "type" "fscaleb") >>> +   (set_attr "mode" "")]) >>>   >>>   ;; >>>   ;;  ................... >>> diff --git a/gcc/testsuite/gcc.target/loongarch/fscaleb.c >>> b/gcc/testsuite/gcc.target/loongarch/fscaleb.c >>> new file mode 100644 >>> index 00000000000..f18470fbb8f >>> --- /dev/null >>> +++ b/gcc/testsuite/gcc.target/loongarch/fscaleb.c >>> @@ -0,0 +1,48 @@ >>> +/* { dg-do compile } */ >>> +/* { dg-options "-O2 -mabi=lp64d -mdouble-float -fno-math-errno" } >>> */ >>> +/* { dg-final { scan-assembler-times "fscaleb\\.s" 3 } } */ >>> +/* { dg-final { scan-assembler-times "fscaleb\\.d" 4 } } */ >>> +/* { dg-final { scan-assembler-times "slli\\.w" 1 } } */ >>> + >>> +double >>> +my_scalbln (double a, long b) >>> +{ >>> +  return __builtin_scalbln (a, b); >>> +} >>> + >>> +double >>> +my_scalbn (double a, int b) >>> +{ >>> +  return __builtin_scalbn (a, b); >>> +} >>> + >>> + >>> +float >>> +my_scalblnf (float a, long b) >>> +{ >>> +  return __builtin_scalblnf (a, b); >>> +} >>> + >>> +float >>> +my_scalbnf (float a, int b) >>> +{ >>> +  return __builtin_scalbnf (a, b); >>> +} >>> + >>> >> I think scalbln/scalblnf/scalbn/scalbnf these four builtin test >> function >> with the macro __FLT_RADIX__ control. >> >> These functions are tested only if the macro __FLT_RADIX__ has a value >> of 2. > LoongArch does not use RESET_FLOAT_FORMAT on SFmode, so __FLT_RADIX__ is > always 2. Ok, I have no more questions