From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 1F90B3858D37 for ; Thu, 16 Nov 2023 09:24:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1F90B3858D37 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=foss.arm.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=foss.arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 1F90B3858D37 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700126642; cv=none; b=VJYBJS97w8Fc9XAuMAxEKhnGosS5kr+HL/CvMs+xPkd3tQ5l2Uo/7lgy7ND0rxYJ6zop2mZWj/0jBMjwZDaLw+KfIfuUpDyIy/dwTrTXDL48cnc02Efgchbxm2B1t0ce85Psdz2m/vmEVtST24LulraKQJhHTdMf26RzHdG6+8A= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700126642; c=relaxed/simple; bh=wq8p5df+1MDeITLnjdxP7Z/qIEOxtqW1MKTsjFWi62k=; h=Message-ID:Date:MIME-Version:Subject:To:From; b=EkeuAE25qjJdhmcptuqjkCpiozjqPMXSI1aVUMQg/37oJZxqE+1cfYD9oH38pW1mJrj579XcSWBzFZga5KlTCFUai29nqq6qeCNqhvz5WBFlMOfkSd+NQX3QKEDPoAJi/7aed2D1QeGho7jYWMOeJaTnEzxM+xAu9nq/c6xRkVo= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D80511595; Thu, 16 Nov 2023 01:24:45 -0800 (PST) Received: from [10.57.41.187] (unknown [10.57.41.187]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 26E3F3F6C4; Thu, 16 Nov 2023 01:23:57 -0800 (PST) Message-ID: Date: Thu, 16 Nov 2023 09:23:57 +0000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/6]AArch64: Add new generic-armv9-a CPU and make it the default for Armv9 Content-Language: en-GB To: Tamar Christina , gcc-patches@gcc.gnu.org Cc: nd@arm.com, Richard.Earnshaw@arm.com, Marcus.Shawcroft@arm.com, Kyrylo.Tkachov@arm.com, richard.sandiford@arm.com References: From: Richard Earnshaw In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3494.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,KAM_LOTSOFHASH,KAM_NUMSUBJECT,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 15/11/2023 17:08, Tamar Christina wrote: > Hi All, > > This patch adds a new generic scheduling model "generic-armv9-a" and makes it > the default for all Armv9 architectures. > > -mcpu=generic and -mtune=generic is kept around for those that really want the > deprecated cost model. > > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. > > Ok for master? > > Thanks, > Tamar > > gcc/ChangeLog: > > PR target/111370 > * config/aarch64/aarch64-arches.def (armv9-a, armv9.1-a, armv9.2-a, > armv9.3-a): Update to generic-armv9-a. > * config/aarch64/aarch64-cores.def (generic-armv9-a): New. > * config/aarch64/aarch64-tune.md: Regenerate. > * config/aarch64/aarch64.cc: Include generic_armv9_a.h. > * config/aarch64/tuning_models/generic_armv9_a.h: New file. OK, but see the comment on patch 3 about 'generic'. R. > > --- inline copy of patch -- > diff --git a/gcc/config/aarch64/aarch64-arches.def b/gcc/config/aarch64/aarch64-arches.def > index f89e4ea1f48acc2875c9a834d93d94c94163cddc..6b9a19c490ba0b35082077e877b19906138f039b 100644 > --- a/gcc/config/aarch64/aarch64-arches.def > +++ b/gcc/config/aarch64/aarch64-arches.def > @@ -40,9 +40,9 @@ AARCH64_ARCH("armv8.6-a", generic_armv8_a, V8_6A, 8, (V8_5A, I8MM, BF > AARCH64_ARCH("armv8.7-a", generic_armv8_a, V8_7A, 8, (V8_6A, LS64)) > AARCH64_ARCH("armv8.8-a", generic_armv8_a, V8_8A, 8, (V8_7A, MOPS)) > AARCH64_ARCH("armv8-r", generic_armv8_a, V8R , 8, (V8_4A)) > -AARCH64_ARCH("armv9-a", generic, V9A , 9, (V8_5A, SVE2)) > -AARCH64_ARCH("armv9.1-a", generic, V9_1A, 9, (V8_6A, V9A)) > -AARCH64_ARCH("armv9.2-a", generic, V9_2A, 9, (V8_7A, V9_1A)) > -AARCH64_ARCH("armv9.3-a", generic, V9_3A, 9, (V8_8A, V9_2A)) > +AARCH64_ARCH("armv9-a", generic_armv9_a, V9A , 9, (V8_5A, SVE2)) > +AARCH64_ARCH("armv9.1-a", generic_armv9_a, V9_1A, 9, (V8_6A, V9A)) > +AARCH64_ARCH("armv9.2-a", generic_armv9_a, V9_2A, 9, (V8_7A, V9_1A)) > +AARCH64_ARCH("armv9.3-a", generic_armv9_a, V9_3A, 9, (V8_8A, V9_2A)) > > #undef AARCH64_ARCH > diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def > index 30f4dd04ed71823bc34c0c405d49963b6b2d1375..16752b77f4baf8d1aa8a5406826aa29e367120c5 100644 > --- a/gcc/config/aarch64/aarch64-cores.def > +++ b/gcc/config/aarch64/aarch64-cores.def > @@ -191,6 +191,7 @@ AARCH64_CORE("demeter", demeter, cortexa57, V9A, (I8MM, BF16, SVE2_BITPERM, RNG, > > /* Generic Architecture Processors. */ > AARCH64_CORE("generic", generic, cortexa53, V8A, (), generic, 0x0, 0x0, -1) > -AARCH64_CORE("generic-armv8-a", generic_armv8_a, cortexa53, V8A, (), generic_armv8_a, 0x0, 0x0, -1) > +AARCH64_CORE("generic-armv8-a", generic_armv8_a, cortexa53, V8A, (), generic_armv8_a, 0x0, 0x0, -1) > +AARCH64_CORE("generic-armv9-a", generic_armv9_a, cortexa53, V9A, (), generic_armv9_a, 0x0, 0x0, -1) > > #undef AARCH64_CORE > diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md > index 0a32056f255de455f47a0b7395dfef0af84c6b5e..61bb85211252970f0a0526929d6b88353bdd930f 100644 > --- a/gcc/config/aarch64/aarch64-tune.md > +++ b/gcc/config/aarch64/aarch64-tune.md > @@ -1,5 +1,5 @@ > ;; -*- buffer-read-only: t -*- > ;; Generated automatically by gentune.sh from aarch64-cores.def > (define_attr "tune" > - "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,ampere1a,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,cortexx1c,neoversen1,ares,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,neoversev1,zeus,neoverse512tvb,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa520,cortexa710,cortexa715,cortexa720,cortexx2,cortexx3,cortexx4,neoversen2,neoversev2,demeter,generic,generic_armv8_a" > + "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,ampere1,ampere1a,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,cortexx1c,neoversen1,ares,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,neoversev1,zeus,neoverse512tvb,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa520,cortexa710,cortexa715,cortexa720,cortexx2,cortexx3,cortexx4,neoversen2,neoversev2,demeter,generic,generic_armv8_a,generic_armv9_a" > (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) > diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc > index 08635e0df9cfa02286f3950383a32f6f93d1b4e0..5bed5f84cef242ec01f8510c76a450f81a985521 100644 > --- a/gcc/config/aarch64/aarch64.cc > +++ b/gcc/config/aarch64/aarch64.cc > @@ -356,6 +356,7 @@ static const struct aarch64_flag_desc aarch64_tuning_flags[] = > /* Tuning parameters. */ > #include "tuning_models/generic.h" > #include "tuning_models/generic_armv8_a.h" > +#include "tuning_models/generic_armv9_a.h" > #include "tuning_models/cortexa35.h" > #include "tuning_models/cortexa53.h" > #include "tuning_models/cortexa57.h" > diff --git a/gcc/config/aarch64/tuning_models/generic_armv9_a.h b/gcc/config/aarch64/tuning_models/generic_armv9_a.h > new file mode 100644 > index 0000000000000000000000000000000000000000..c017468592a9dba74ddd432247aaf51a70bb34b5 > --- /dev/null > +++ b/gcc/config/aarch64/tuning_models/generic_armv9_a.h > @@ -0,0 +1,245 @@ > +/* Tuning model description for AArch64 architecture. > + Copyright (C) 2009-2023 Free Software Foundation, Inc. > + > + This file is part of GCC. > + > + GCC is free software; you can redistribute it and/or modify it > + under the terms of the GNU General Public License as published by > + the Free Software Foundation; either version 3, or (at your option) > + any later version. > + > + GCC is distributed in the hope that it will be useful, but > + WITHOUT ANY WARRANTY; without even the implied warranty of > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + General Public License for more details. > + > + You should have received a copy of the GNU General Public License > + along with GCC; see the file COPYING3. If not see > + . */ > + > +#ifndef GCC_AARCH64_H_GENERIC_ARMV9_A > +#define GCC_AARCH64_H_GENERIC_ARMV9_A > + > +#include "generic.h" > +#include "generic_armv8_a.h" > + > +static const struct cpu_addrcost_table generic_armv9_a_addrcost_table = > +{ > + { > + 1, /* hi */ > + 0, /* si */ > + 0, /* di */ > + 1, /* ti */ > + }, > + 0, /* pre_modify */ > + 0, /* post_modify */ > + 2, /* post_modify_ld3_st3 */ > + 2, /* post_modify_ld4_st4 */ > + 0, /* register_offset */ > + 0, /* register_sextend */ > + 0, /* register_zextend */ > + 0 /* imm_offset */ > +}; > + > +static const struct cpu_regmove_cost generic_armv9_a_regmove_cost = > +{ > + 1, /* GP2GP */ > + /* Spilling to int<->fp instead of memory is recommended so set > + realistic costs compared to memmov_cost. */ > + 3, /* GP2FP */ > + 2, /* FP2GP */ > + 2 /* FP2FP */ > +}; > + > +static const advsimd_vec_cost generic_armv9_a_advsimd_vector_cost = > +{ > + 2, /* int_stmt_cost */ > + 2, /* fp_stmt_cost */ > + 2, /* ld2_st2_permute_cost */ > + 2, /* ld3_st3_permute_cost */ > + 3, /* ld4_st4_permute_cost */ > + 3, /* permute_cost */ > + 4, /* reduc_i8_cost */ > + 4, /* reduc_i16_cost */ > + 2, /* reduc_i32_cost */ > + 2, /* reduc_i64_cost */ > + 6, /* reduc_f16_cost */ > + 4, /* reduc_f32_cost */ > + 2, /* reduc_f64_cost */ > + 2, /* store_elt_extra_cost */ > + /* This value is just inherited from the Cortex-A57 table. */ > + 8, /* vec_to_scalar_cost */ > + /* This depends very much on what the scalar value is and > + where it comes from. E.g. some constants take two dependent > + instructions or a load, while others might be moved from a GPR. > + 4 seems to be a reasonable compromise in practice. */ > + 4, /* scalar_to_vec_cost */ > + 4, /* align_load_cost */ > + 4, /* unalign_load_cost */ > + /* Although stores have a latency of 2 and compete for the > + vector pipes, in practice it's better not to model that. */ > + 1, /* unalign_store_cost */ > + 1 /* store_cost */ > +}; > + > +static const sve_vec_cost generic_armv9_a_sve_vector_cost = > +{ > + { > + 2, /* int_stmt_cost */ > + 2, /* fp_stmt_cost */ > + 3, /* ld2_st2_permute_cost */ > + 4, /* ld3_st3_permute_cost */ > + 4, /* ld4_st4_permute_cost */ > + 3, /* permute_cost */ > + /* Theoretically, a reduction involving 15 scalar ADDs could > + complete in ~5 cycles and would have a cost of 15. [SU]ADDV > + completes in 11 cycles, so give it a cost of 15 + 6. */ > + 21, /* reduc_i8_cost */ > + /* Likewise for 7 scalar ADDs (~3 cycles) vs. 9: 7 + 6. */ > + 13, /* reduc_i16_cost */ > + /* Likewise for 3 scalar ADDs (~2 cycles) vs. 8: 3 + 6. */ > + 9, /* reduc_i32_cost */ > + /* Likewise for 1 scalar ADD (~1 cycles) vs. 2: 1 + 1. */ > + 2, /* reduc_i64_cost */ > + /* Theoretically, a reduction involving 7 scalar FADDs could > + complete in ~8 cycles and would have a cost of 14. FADDV > + completes in 6 cycles, so give it a cost of 14 - 2. */ > + 12, /* reduc_f16_cost */ > + /* Likewise for 3 scalar FADDs (~4 cycles) vs. 4: 6 - 0. */ > + 6, /* reduc_f32_cost */ > + /* Likewise for 1 scalar FADD (~2 cycles) vs. 2: 2 - 0. */ > + 2, /* reduc_f64_cost */ > + 2, /* store_elt_extra_cost */ > + /* This value is just inherited from the Cortex-A57 table. */ > + 8, /* vec_to_scalar_cost */ > + /* See the comment above the Advanced SIMD versions. */ > + 4, /* scalar_to_vec_cost */ > + 4, /* align_load_cost */ > + 4, /* unalign_load_cost */ > + /* Although stores have a latency of 2 and compete for the > + vector pipes, in practice it's better not to model that. */ > + 1, /* unalign_store_cost */ > + 1 /* store_cost */ > + }, > + 3, /* clast_cost */ > + 10, /* fadda_f16_cost */ > + 6, /* fadda_f32_cost */ > + 4, /* fadda_f64_cost */ > + /* A strided Advanced SIMD x64 load would take two parallel FP loads > + (8 cycles) plus an insertion (2 cycles). Assume a 64-bit SVE gather > + is 1 cycle more. The Advanced SIMD version is costed as 2 scalar loads > + (cost 8) and a vec_construct (cost 2). Add a full vector operation > + (cost 2) to that, to avoid the difference being lost in rounding. > + > + There is no easy comparison between a strided Advanced SIMD x32 load > + and an SVE 32-bit gather, but cost an SVE 32-bit gather as 1 vector > + operation more than a 64-bit gather. */ > + 14, /* gather_load_x32_cost */ > + 12, /* gather_load_x64_cost */ > + 3 /* scatter_store_elt_cost */ > +}; > + > +static const aarch64_scalar_vec_issue_info generic_armv9_a_scalar_issue_info = > +{ > + 3, /* loads_stores_per_cycle */ > + 2, /* stores_per_cycle */ > + 4, /* general_ops_per_cycle */ > + 0, /* fp_simd_load_general_ops */ > + 1 /* fp_simd_store_general_ops */ > +}; > + > +static const aarch64_advsimd_vec_issue_info generic_armv9_a_advsimd_issue_info = > +{ > + { > + 3, /* loads_stores_per_cycle */ > + 2, /* stores_per_cycle */ > + 2, /* general_ops_per_cycle */ > + 0, /* fp_simd_load_general_ops */ > + 1 /* fp_simd_store_general_ops */ > + }, > + 2, /* ld2_st2_general_ops */ > + 2, /* ld3_st3_general_ops */ > + 3 /* ld4_st4_general_ops */ > +}; > + > +static const aarch64_sve_vec_issue_info generic_armv9_a_sve_issue_info = > +{ > + { > + { > + 3, /* loads_per_cycle */ > + 2, /* stores_per_cycle */ > + 2, /* general_ops_per_cycle */ > + 0, /* fp_simd_load_general_ops */ > + 1 /* fp_simd_store_general_ops */ > + }, > + 2, /* ld2_st2_general_ops */ > + 3, /* ld3_st3_general_ops */ > + 3 /* ld4_st4_general_ops */ > + }, > + 2, /* pred_ops_per_cycle */ > + 2, /* while_pred_ops */ > + 2, /* int_cmp_pred_ops */ > + 1, /* fp_cmp_pred_ops */ > + 1, /* gather_scatter_pair_general_ops */ > + 1 /* gather_scatter_pair_pred_ops */ > +}; > + > +static const aarch64_vec_issue_info generic_armv9_a_vec_issue_info = > +{ > + &generic_armv9_a_scalar_issue_info, > + &generic_armv9_a_advsimd_issue_info, > + &generic_armv9_a_sve_issue_info > +}; > + > +/* Neoverse N2 costs for vector insn classes. */ > +static const struct cpu_vector_cost generic_armv9_a_vector_cost = > +{ > + 1, /* scalar_int_stmt_cost */ > + 2, /* scalar_fp_stmt_cost */ > + 4, /* scalar_load_cost */ > + 1, /* scalar_store_cost */ > + 1, /* cond_taken_branch_cost */ > + 1, /* cond_not_taken_branch_cost */ > + &generic_armv9_a_advsimd_vector_cost, /* advsimd */ > + &generic_armv9_a_sve_vector_cost, /* sve */ > + &generic_armv9_a_vec_issue_info /* issue_info */ > +}; > + > +static const struct tune_params generic_armv9_a_tunings = > +{ > + &cortexa76_extra_costs, > + &generic_armv9_a_addrcost_table, > + &generic_armv9_a_regmove_cost, > + &generic_armv9_a_vector_cost, > + &generic_branch_cost, > + &generic_approx_modes, > + SVE_SCALABLE, /* sve_width */ > + { 4, /* load_int. */ > + 1, /* store_int. */ > + 6, /* load_fp. */ > + 2, /* store_fp. */ > + 6, /* load_pred. */ > + 1 /* store_pred. */ > + }, /* memmov_cost. */ > + 3, /* issue_rate */ > + (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_CMP_BRANCH), /* fusible_ops */ > + "32:16", /* function_align. */ > + "4", /* jump_align. */ > + "32:16", /* loop_align. */ > + 2, /* int_reassoc_width. */ > + 4, /* fp_reassoc_width. */ > + 1, /* fma_reassoc_width. */ > + 2, /* vec_reassoc_width. */ > + 2, /* min_div_recip_mul_sf. */ > + 2, /* min_div_recip_mul_df. */ > + 0, /* max_case_values. */ > + tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ > + (AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND > + | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS > + | AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT), /* tune_flags. */ > + &generic_prefetch_tune, > + AARCH64_LDP_STP_POLICY_ALWAYS, /* ldp_policy_model. */ > + AARCH64_LDP_STP_POLICY_ALWAYS /* stp_policy_model. */ > +}; > + > +#endif /* GCC_AARCH64_H_GENERIC_ARMV9_A. */ > > > >