From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id 0821F3858D1E for ; Sat, 27 Apr 2024 05:19:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0821F3858D1E Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=xry111.site Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xry111.site ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 0821F3858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=89.208.246.23 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1714195150; cv=none; b=GlS0anTqwnxh/So0RMnzaPrB4HGaZ9bLSoUfVU8s7H74Wo7tfb+H08b1kQRr514RqOELozoHEUWphOZE+xTOX8W8p/BQcpAjpAptVfHXXRrGd+TD1/5iQLE68UkINwht+8YL63QxSTTXtiJ/y/AZG5YsxpNevc9XqtG0fUVJEhg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1714195150; c=relaxed/simple; bh=8sb5Mjh5j0koq8RuO6HhektZ8OsXkuGJMntm9g1jzAg=; h=DKIM-Signature:Message-ID:Subject:From:To:Date:MIME-Version; b=lG7vHjVsPb1SwqZVnXmi245T9ILAjyZJDVL2NoKpIemjUFAipf6NSHJBJzDBUI/6+WpMbPWPKcRMi/VF0nI/eWbINDBxtTMDXvwKqFLGuTuARrt0HXRKn6/U1INBxnwWwNV9IyJLhoTIeLiQMEp/HlZ/ShAV5ul3Y8EtXtOFThc= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xry111.site; s=default; t=1714195144; bh=8sb5Mjh5j0koq8RuO6HhektZ8OsXkuGJMntm9g1jzAg=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=ageA1SY2zPD9OnSwR32ynOiNygrE6mDR4QeHX5QItsyuBDOxMg7G5CFj1M2E9wHK1 /A1AkLoRx0ypGFRYQQYVtmBvj58biK+W3WIv7zwcrB69RmDB291ykXi/msTfeGDsw8 kZLD9qtY7b2wTCSiKK4UScGXjvys/VFyiThXV+lA= Received: from [IPv6:240e:358:1198:0:dc73:854d:832e:4] (unknown [IPv6:240e:358:1198:0:dc73:854d:832e:4]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id A64946692C; Sat, 27 Apr 2024 01:19:00 -0400 (EDT) Message-ID: Subject: Pushed: [PATCH] LoongArch: Add constraints for bit string operation define_insn_and_split's [PR114861] From: Xi Ruoyao To: Lulu Cheng , gcc-patches@gcc.gnu.org Cc: i@xen0n.name, xuchenghua@loongson.cn Date: Sat, 27 Apr 2024 13:18:56 +0800 In-Reply-To: <7492159f-967b-20f1-e216-9216898b637b@loongson.cn> References: <20240426135241.893321-1-xry111@xry111.site> <7492159f-967b-20f1-e216-9216898b637b@loongson.cn> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.1 MIME-Version: 1.0 X-Spam-Status: No, score=-7.7 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,LIKELY_SPAM_FROM,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Sat, 2024-04-27 at 11:04 +0800, Lulu Cheng wrote: > LGTM! >=20 > Thanks. Pushed r15-11 and r14-10142. > =E5=9C=A8 2024/4/26 =E4=B8=8B=E5=8D=889:52, Xi Ruoyao =E5=86=99=E9=81=93: > > Without the constrants, the compiler attempts to use a stack slot as th= e > > target, causing an ICE building the kernel with -Os: > >=20 > > =C2=A0=C2=A0=C2=A0=C2=A0 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c:3144:1: > > =C2=A0=C2=A0=C2=A0=C2=A0 error: could not split insn > > =C2=A0=C2=A0=C2=A0=C2=A0 (insn:TI 1764 67 1745 > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (set (mem/c:DI (reg/f:DI 3 $r3) [7= 07 %sfp+-80 S8 A64]) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (and= :DI (reg/v:DI 28 $r28 [orig:422 raster_config ] [422]) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (const_int -50331649 [0xfffff= ffffcffffff]))) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 "drivers/gpu/drm/amd/amdgpu/gfx_v6= _0.c":1386:21 111 > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 {*bstrins_di_for_mask} > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (nil)) > >=20 > > Add these constrants to fix the issue. > >=20 > > gcc/ChangeLog: > >=20 > > PR target/114861 > > * config/loongarch/loongarch.md (bstrins__for_mask): Add > > constraints for operands. > > (bstrins__for_ior_mask): Likewise. > >=20 > > gcc/testsuite/ChangeLog: > >=20 > > PR target/114861 > > * gcc.target/loongarch/pr114861.c: New test. > > --- > > =C2=A0 gcc/config/loongarch/loongarch.md=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 16 ++++---- > > =C2=A0 gcc/testsuite/gcc.target/loongarch/pr114861.c | 39 +++++++++++++= ++++++ > > =C2=A0 2 files changed, 47 insertions(+), 8 deletions(-) > > =C2=A0 create mode 100644 gcc/testsuite/gcc.target/loongarch/pr114861.c > >=20 > > diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/l= oongarch.md > > index a316c8fb820..5c80c169cbf 100644 > > --- a/gcc/config/loongarch/loongarch.md > > +++ b/gcc/config/loongarch/loongarch.md > > @@ -1543,9 +1543,9 @@ (define_insn "and3_extended" > > =C2=A0=C2=A0=C2=A0=C2=A0 (set_attr "mode" "")]) > > =C2=A0=20 > > =C2=A0 (define_insn_and_split "*bstrins__for_mask" > > -=C2=A0 [(set (match_operand:GPR 0 "register_operand") > > - (and:GPR (match_operand:GPR 1 "register_operand") > > - (match_operand:GPR 2 "ins_zero_bitmask_operand")))] > > +=C2=A0 [(set (match_operand:GPR 0 "register_operand" "=3Dr") > > + (and:GPR (match_operand:GPR 1 "register_operand" "r") > > + (match_operand:GPR 2 "ins_zero_bitmask_operand" "i")))] > > =C2=A0=C2=A0=C2=A0 "" > > =C2=A0=C2=A0=C2=A0 "#" > > =C2=A0=C2=A0=C2=A0 "" > > @@ -1563,11 +1563,11 @@ (define_insn_and_split "*bstrins__for_mas= k" > > =C2=A0=C2=A0=C2=A0 }) > > =C2=A0=20 > > =C2=A0 (define_insn_and_split "*bstrins__for_ior_mask" > > -=C2=A0 [(set (match_operand:GPR 0 "register_operand") > > - (ior:GPR (and:GPR (match_operand:GPR 1 "register_operand") > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 (match_operand:GPR 2 "const_int_operand")) > > - (and:GPR (match_operand:GPR 3 "register_operand") > > - =C2=A0 (match_operand:GPR 4 "const_int_operand"))))] > > +=C2=A0 [(set (match_operand:GPR 0 "register_operand" "=3Dr") > > + (ior:GPR (and:GPR (match_operand:GPR 1 "register_operand" "r") > > + =C2=A0 (match_operand:GPR 2 "const_int_operand" "i")) > > + (and:GPR (match_operand:GPR 3 "register_operand" "r") > > + =C2=A0 (match_operand:GPR 4 "const_int_operand" "i"))))] > > =C2=A0=C2=A0=C2=A0 "loongarch_pre_reload_split () > > =C2=A0=C2=A0=C2=A0=C2=A0 && loongarch_use_bstrins_for_ior_with_mask (mode, operands)" > > =C2=A0=C2=A0=C2=A0 "#" > > diff --git a/gcc/testsuite/gcc.target/loongarch/pr114861.c b/gcc/testsu= ite/gcc.target/loongarch/pr114861.c > > new file mode 100644 > > index 00000000000..e6507c406b9 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/loongarch/pr114861.c > > @@ -0,0 +1,39 @@ > > +/* PR114861: ICE building the kernel with -Os > > +=C2=A0=C2=A0 Reduced from linux/fs/ntfs3/attrib.c at revision c942a0cd= 3603.=C2=A0 */ > > +/* { dg-do compile } */ > > +/* { dg-options "-Os -march=3Dloongarch64 -msoft-float -mabi=3Dlp64s" = } */ > > + > > +long evcn, attr_collapse_range_vbo, attr_collapse_range_bytes; > > +unsigned short flags; > > +int attr_collapse_range_ni_0_0; > > +int *attr_collapse_range_mi; > > +unsigned attr_collapse_range_svcn, attr_collapse_range_vcn1; > > +void ni_insert_nonresident (unsigned, unsigned short, int **); > > +int mi_pack_runs (int); > > +int > > +attr_collapse_range (void) > > +{ > > +=C2=A0 _Bool __trans_tmp_1; > > +=C2=A0 int run =3D attr_collapse_range_ni_0_0; > > +=C2=A0 unsigned evcn1, vcn, end; > > +=C2=A0 short a_flags =3D flags; > > +=C2=A0 __trans_tmp_1 =3D flags & (32768 | 1); > > +=C2=A0 if (__trans_tmp_1) > > +=C2=A0=C2=A0=C2=A0 return 2; > > +=C2=A0 vcn =3D attr_collapse_range_vbo; > > +=C2=A0 end =3D attr_collapse_range_bytes; > > +=C2=A0 evcn1 =3D evcn; > > +=C2=A0 for (;;) > > +=C2=A0=C2=A0=C2=A0 if (attr_collapse_range_svcn >=3D end) > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 { > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 unsigned eat, next_svcn =3D= mi_pack_runs (42); > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 attr_collapse_range_vcn1 = =3D (vcn ? vcn : attr_collapse_range_svcn); > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 eat =3D (0 < end) - attr_co= llapse_range_vcn1; > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 mi_pack_runs (run - eat); > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (next_svcn + eat) > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ni_insert_nonre= sident (evcn1 - eat - next_svcn, a_flags, > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 &attr_collapse_range_mi); > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } > > +=C2=A0=C2=A0=C2=A0 else > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return 42; > > +} >=20 --=20 Xi Ruoyao School of Aerospace Science and Technology, Xidian University