Re: [patch, ARM] PR48250, rehaul arm_legitimize_reload_address()

[Richard Sandiford <richard.sandiford@linaro.org>]

Hi Chung-Lin,

I'm seeing an ICE with this patch, specifically;

Chung-Lin Tang <cltang@codesourcery.com> writes:
> +      if (coproc_p)
> +	low = SIGN_MAG_LOW_ADDR_BITS (val, 10);

We generate:

Reload 1: reload_out (V4SI) = (mem/c:V4SI (plus:SI (plus:SI (reg/f:SI 11 fp)
                                                            (const_int -6144 [0xffffffffffffe800]))
                                                        (const_int 1020 [0x3fc])) [43 %sfp+-5024 S16 A64])

but 1020 isn't a legitimate offset for V4SI:

  /* For quad modes, we restrict the constant offset to be slightly less
     than what the instruction format permits.  We do this because for
     quad mode moves, we will actually decompose them into two separate
     double-mode reads or writes.  INDEX must therefore be a valid
     (double-mode) offset and so should INDEX+8.  */
  if (TARGET_NEON && VALID_NEON_QREG_MODE (mode))
    return (code == CONST_INT
	    && INTVAL (index) < 1016
	    && INTVAL (index) > -1024
	    && (INTVAL (index) & 3) == 0);

A simple "fix" would be to use 9 instead of 10, but something a little
more subtle might be preferred :-)

Richard