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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by AM7EUR03FT055.mail.protection.outlook.com (100.127.141.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5901.17 via Frontend Transport; Fri, 9 Dec 2022 14:16:03 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX04.Arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Fri, 9 Dec 2022 14:16:01 +0000 Received: from e124257 (10.34.105.24) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16 via Frontend Transport; Fri, 9 Dec 2022 14:16:01 +0000 From: Andrea Corallo To: Richard Earnshaw CC: Andrea Corallo via Gcc-patches , "Richard Earnshaw" , nd Subject: [PATCH 10/15 V5] arm: Implement cortex-M return signing address codegen References: <2d22c659-1452-6302-0dd0-270763510950@foss.arm.com> Date: Fri, 9 Dec 2022 15:16:00 +0100 In-Reply-To: <2d22c659-1452-6302-0dd0-270763510950@foss.arm.com> (Richard Earnshaw's message of "Mon, 5 Dec 2022 16:38:34 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2.50 (gnu/linux) MIME-Version: 1.0 Content-Type: multipart/mixed; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2022 14:16:21.5046 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d514d776-b75d-4c8e-1324-08dad9eff289 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT065.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR08MB5876 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --=-=-= Content-Type: text/plain Hi Richard, thanks for reviewing. Richard Earnshaw writes: > On 07/11/2022 08:57, Andrea Corallo via Gcc-patches wrote: >> Hi all, >> please find attached the lastest version of this patch incorporating >> some >> more improvents. Feel free to ignore V3. >> Best Regards >> Andrea >> > >> As part of previous upstream suggestions a test for varargs has been >> added and '-mtpcs-frame' is deemed being incompatible with this return >> signing address feature being introduced. > > I don't see any check for the tpcs-frame incompatibility? What > happens if a user does combine the options? Check added. > gcc/Changelog > > 2021-11-03 Andrea Corallo > > * config/arm/arm.h (arm_arch8m_main): Declare it. > * config/arm/arm.cc (arm_arch8m_main): Define it. > (arm_option_reconfigure_globals): Set arm_arch8m_main. > (arm_compute_frame_layout, arm_expand_prologue) > (thumb2_expand_return, arm_expand_epilogue) > (arm_conditional_register_usage): Update for pac codegen. > (arm_current_function_pac_enabled_p): New function. > * config/arm/arm.md (pac_ip_lr_sp, pacbti_ip_lr_sp, aut_ip_lr_sp): > Add new patterns. > * config/arm/unspecs.md (UNSPEC_PAC_IP_LR_SP) > (UNSPEC_PACBTI_IP_LR_SP, UNSPEC_AUT_IP_LR_SP): Add unspecs. > > You're missing an entry for aarch_bti_enabled () - yes I realize > that's just a placeholder at present and will be fully defined in > patch 12. Fixed > +static bool > +aarch_bti_enabled () > +{ > + return false; > +} > + > > No comment on this function (and in patch 12 it moves to a different > location). It would be best to have it in the right place at this > point in time. > > + clobber_ip = (IS_NESTED (func_type) > + && (((TARGET_APCS_FRAME && frame_pointer_needed && > TARGET_ARM) > + || ((flag_stack_check == STATIC_BUILTIN_STACK_CHECK > + || flag_stack_clash_protection) > + && !df_regs_ever_live_p (LR_REGNUM) > + && arm_r3_live_at_start_p ())) > + || (arm_current_function_pac_enabled_p ()))); > > Redundant parenthesis around arm_current_function_pac_enabled_p () call. Fixed > + gcc_assert(arm_compute_static_chain_stack_bytes() == 4 > + || arm_current_function_pac_enabled_p ()); > > I wonder if this assert is now really serving a useful purpose. I'd > consider removing it. Removed > @@ -27309,7 +27340,7 @@ thumb2_expand_return (bool simple_return) > to assert it for now to ensure that future code changes do not silently > change this behavior. */ > gcc_assert (!IS_CMSE_ENTRY (arm_current_func_type ())); > - if (num_regs == 1) > + if (num_regs == 1 && !arm_current_function_pac_enabled_p ()) > { > rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2)); > rtx reg = gen_rtx_REG (SImode, PC_REGNUM); > @@ -27324,10 +27355,20 @@ thumb2_expand_return (bool simple_return) > } > else > { > - saved_regs_mask &= ~ (1 << LR_REGNUM); > - saved_regs_mask |= (1 << PC_REGNUM); > - arm_emit_multi_reg_pop (saved_regs_mask); > - } > + if (arm_current_function_pac_enabled_p ()) > + { > + gcc_assert (!(saved_regs_mask & (1 << PC_REGNUM))); > + arm_emit_multi_reg_pop (saved_regs_mask); > + emit_insn (gen_aut_nop ()); > + emit_jump_insn (simple_return_rtx); > + } > + else > + { > + saved_regs_mask &= ~ (1 << LR_REGNUM); > + saved_regs_mask |= (1 << PC_REGNUM); > + arm_emit_multi_reg_pop (saved_regs_mask); > + } > + } > } > else > > The logic for these blocks would, I think, be better expressed as > > if (pac_enabled) > ... > else if (num_regs == 1) > ... // existing code > else > ... // existing code Done > Also, I think (out of an abundance of caution) we really need a > scheduling barrier placed before calls to gen_aut_nop() pattern is > emitted, to ensure that the scheduler never tries to move this > instruction away from the position we place it. Use gen_blockage() > for that (see TARGET_SCHED_PROLOG). Alternatively, we could make the > UNSPEC_PAC_NOP an unspec_volatile, which has the same effect (IIRC) > without needing an additional insn - if you use this approach, then > please make sure this is explained in a comment. > > +(define_insn "pacbti_nop" > + [(set (reg:SI IP_REGNUM) > + (unspec:SI [(reg:SI SP_REGNUM) (reg:SI LR_REGNUM)] > + UNSPEC_PACBTI_NOP))] > + "arm_arch8m_main" > + "pacbti\t%|ip, %|lr, %|sp" > + [(set_attr "conds" "unconditional")]) > > The additional side-effect of this being a BTI landing pad means that > we mustn't move any other instruction before it. So I think this > needs to be an unspec_volatile as well. Done > On the tests, they are OK as they stand, but we lack anything that > will be tested when suitable hardware is unavailable (all tests are > "dg-do run"). Can we please have some compile-only tests as well? Added three compile only tests. Please find attached the latest version of the patch. BR Andrea --=-=-= Content-Type: text/plain; charset="utf-8" Content-Disposition: attachment; filename="0001-PATCH-10-15-arm-Implement-cortex-M-return-signing-ad.patch" >From 56b7b3336142c0499826e43139a21483296467ef Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Thu, 20 Jan 2022 15:36:23 +0100 Subject: [PATCH] [PATCH 10/15] arm: Implement cortex-M return signing address codegen Hi all, this patch enables address return signature and verification based on Armv8.1-M Pointer Authentication [1]. To sign the return address, we use the PAC R12, LR, SP instruction upon function entry. This is signing LR using SP and storing the result in R12. R12 will be pushed into the stack. During function epilogue R12 will be popped and AUT R12, LR, SP will be used to verify that the content of LR is still valid before return. Here an example of PAC instrumented function prologue and epilogue: void foo (void); int main() { foo (); return 0; } Compiled with '-march=armv8.1-m.main -mbranch-protection=pac-ret -mthumb' translates into: main: pac ip, lr, sp push {r3, r7, ip, lr} add r7, sp, #0 bl foo movs r3, #0 mov r0, r3 pop {r3, r7, ip, lr} aut ip, lr, sp bx lr The patch also takes care of generating a PACBTI instruction in place of the sequence BTI+PAC when Branch Target Identification is enabled contextually. Ex. the previous example compiled with '-march=armv8.1-m.main -mbranch-protection=pac-ret+bti -mthumb' translates into: main: pacbti ip, lr, sp push {r3, r7, ip, lr} add r7, sp, #0 bl foo movs r3, #0 mov r0, r3 pop {r3, r7, ip, lr} aut ip, lr, sp bx lr As part of previous upstream suggestions a test for varargs has been added and '-mtpcs-frame' is deemed being incompatible with this return signing address feature being introduced. [1] gcc/Changelog 2021-11-03 Andrea Corallo * config/arm/arm.h (arm_arch8m_main): Declare it. * config/arm/arm.cc (arm_arch8m_main): Define it. (arm_option_reconfigure_globals): Set arm_arch8m_main. (arm_compute_frame_layout, arm_expand_prologue) (thumb2_expand_return, arm_expand_epilogue) (arm_conditional_register_usage): Update for pac codegen. (arm_current_function_pac_enabled_p): New function. (aarch_bti_enabled) New function. * config/arm/arm.md (pac_ip_lr_sp, pacbti_ip_lr_sp, aut_ip_lr_sp): Add new patterns. * config/arm/unspecs.md (UNSPEC_PAC_NOP) (VUNSPEC_PACBTI_NOP, VUNSPEC_AUT_NOP): Add unspecs. gcc/testsuite/Changelog 2021-11-03 Andrea Corallo * gcc.target/arm/pac.h : New file. * gcc.target/arm/pac-1.c : New test case. * gcc.target/arm/pac-2.c : Likewise. * gcc.target/arm/pac-3.c : Likewise. * gcc.target/arm/pac-4.c : Likewise. * gcc.target/arm/pac-5.c : Likewise. * gcc.target/arm/pac-6.c : Likewise. * gcc.target/arm/pac-7.c : Likewise. * gcc.target/arm/pac-8.c : Likewise. * gcc.target/arm/pac-9.c : Likewise. * gcc.target/arm/pac-10.c : Likewise. * gcc.target/arm/pac-11.c : Likewise. --- gcc/config/arm/arm-protos.h | 1 + gcc/config/arm/arm.cc | 74 +++++++++++++++++++++++---- gcc/config/arm/arm.h | 4 ++ gcc/config/arm/arm.md | 23 +++++++++ gcc/config/arm/unspecs.md | 3 ++ gcc/testsuite/gcc.target/arm/pac-1.c | 11 ++++ gcc/testsuite/gcc.target/arm/pac-10.c | 10 ++++ gcc/testsuite/gcc.target/arm/pac-11.c | 10 ++++ gcc/testsuite/gcc.target/arm/pac-2.c | 11 ++++ gcc/testsuite/gcc.target/arm/pac-3.c | 11 ++++ gcc/testsuite/gcc.target/arm/pac-4.c | 10 ++++ gcc/testsuite/gcc.target/arm/pac-5.c | 28 ++++++++++ gcc/testsuite/gcc.target/arm/pac-6.c | 18 +++++++ gcc/testsuite/gcc.target/arm/pac-7.c | 32 ++++++++++++ gcc/testsuite/gcc.target/arm/pac-8.c | 34 ++++++++++++ gcc/testsuite/gcc.target/arm/pac-9.c | 11 ++++ gcc/testsuite/gcc.target/arm/pac.h | 17 ++++++ 17 files changed, 299 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/pac-1.c create mode 100644 gcc/testsuite/gcc.target/arm/pac-10.c create mode 100644 gcc/testsuite/gcc.target/arm/pac-11.c create mode 100644 gcc/testsuite/gcc.target/arm/pac-2.c create mode 100644 gcc/testsuite/gcc.target/arm/pac-3.c create mode 100644 gcc/testsuite/gcc.target/arm/pac-4.c create mode 100644 gcc/testsuite/gcc.target/arm/pac-5.c create mode 100644 gcc/testsuite/gcc.target/arm/pac-6.c create mode 100644 gcc/testsuite/gcc.target/arm/pac-7.c create mode 100644 gcc/testsuite/gcc.target/arm/pac-8.c create mode 100644 gcc/testsuite/gcc.target/arm/pac-9.c create mode 100644 gcc/testsuite/gcc.target/arm/pac.h diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 6e6bf147e9c..d97a1c3bf56 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -378,6 +378,7 @@ extern int vfp3_const_double_for_bits (rtx); extern void arm_emit_coreregs_64bit_shift (enum rtx_code, rtx, rtx, rtx, rtx, rtx); extern bool arm_fusion_enabled_p (tune_params::fuse_ops); +extern bool arm_current_function_pac_enabled_p (void); extern bool arm_valid_symbolic_address_p (rtx); extern bool arm_validize_comparison (rtx *, rtx *, rtx *); extern bool arm_expand_vector_compare (rtx, rtx_code, rtx, rtx, bool); diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 4ac42e58b90..705364ad13f 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -923,6 +923,11 @@ int arm_arch8_3 = 0; /* Nonzero if this chip supports the ARM Architecture 8.4 extensions. */ int arm_arch8_4 = 0; + +/* Nonzero if this chip supports the ARM Architecture 8-M Mainline + extensions. */ +int arm_arch8m_main = 0; + /* Nonzero if this chip supports the ARM Architecture 8.1-M Mainline extensions. */ int arm_arch8_1m_main = 0; @@ -3205,6 +3210,15 @@ arm_option_override_internal (struct gcc_options *opts, arm_stack_protector_guard_offset = offs; } + if (arm_current_function_pac_enabled_p ()) + { + if (!arm_arch8m_main) + error ("This architecture does not support branch protection " + "instructions"); + if (TARGET_TPCS_FRAME) + error ("Return address signing and %<-mtpcs-frame%> are incompatible."); + } + #ifdef SUBTARGET_OVERRIDE_INTERNAL_OPTIONS SUBTARGET_OVERRIDE_INTERNAL_OPTIONS; #endif @@ -3851,6 +3865,7 @@ arm_option_reconfigure_globals (void) arm_arch_arm_hwdiv = bitmap_bit_p (arm_active_target.isa, isa_bit_adiv); arm_arch_crc = bitmap_bit_p (arm_active_target.isa, isa_bit_crc32); arm_arch_cmse = bitmap_bit_p (arm_active_target.isa, isa_bit_cmse); + arm_arch8m_main = arm_arch7 && arm_arch_cmse; arm_arch_lpae = bitmap_bit_p (arm_active_target.isa, isa_bit_lpae); arm_arch_i8mm = bitmap_bit_p (arm_active_target.isa, isa_bit_i8mm); arm_arch_bf16 = bitmap_bit_p (arm_active_target.isa, isa_bit_bf16); @@ -21227,6 +21242,9 @@ arm_compute_save_core_reg_mask (void) save_reg_mask |= arm_compute_save_reg0_reg12_mask (); + if (arm_current_function_pac_enabled_p ()) + save_reg_mask |= 1 << IP_REGNUM; + /* Decide if we need to save the link register. Interrupt routines have their own banked link register, so they never need to save it. @@ -23528,12 +23546,13 @@ arm_expand_prologue (void) /* The static chain register is the same as the IP register. If it is clobbered when creating the frame, we need to save and restore it. */ - clobber_ip = IS_NESTED (func_type) - && ((TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) - || ((flag_stack_check == STATIC_BUILTIN_STACK_CHECK - || flag_stack_clash_protection) - && !df_regs_ever_live_p (LR_REGNUM) - && arm_r3_live_at_start_p ())); + clobber_ip = (IS_NESTED (func_type) + && (((TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) + || ((flag_stack_check == STATIC_BUILTIN_STACK_CHECK + || flag_stack_clash_protection) + && !df_regs_ever_live_p (LR_REGNUM) + && arm_r3_live_at_start_p ())) + || arm_current_function_pac_enabled_p ())); /* Find somewhere to store IP whilst the frame is being created. We try the following places in order: @@ -23558,7 +23577,6 @@ arm_expand_prologue (void) { rtx addr, dwarf; - gcc_assert(arm_compute_static_chain_stack_bytes() == 4); saved_regs += 4; addr = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); @@ -23609,6 +23627,17 @@ arm_expand_prologue (void) } } + if (arm_current_function_pac_enabled_p ()) + { + /* If IP was clobbered we only emit a PAC instruction as the BTI + one will be added before the push of the clobbered IP (if + necessary) by the bti pass. */ + if (aarch_bti_enabled () && !clobber_ip) + emit_insn (gen_pacbti_nop ()); + else + emit_insn (gen_pac_nop ()); + } + if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) { if (IS_INTERRUPT (func_type)) @@ -27420,7 +27449,14 @@ thumb2_expand_return (bool simple_return) to assert it for now to ensure that future code changes do not silently change this behavior. */ gcc_assert (!IS_CMSE_ENTRY (arm_current_func_type ())); - if (num_regs == 1) + if (arm_current_function_pac_enabled_p ()) + { + gcc_assert (!(saved_regs_mask & (1 << PC_REGNUM))); + arm_emit_multi_reg_pop (saved_regs_mask); + emit_insn (gen_aut_nop ()); + emit_jump_insn (simple_return_rtx); + } + else if (num_regs == 1) { rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2)); rtx reg = gen_rtx_REG (SImode, PC_REGNUM); @@ -27844,7 +27880,8 @@ arm_expand_epilogue (bool really_return) && really_return && crtl->args.pretend_args_size == 0 && saved_regs_mask & (1 << LR_REGNUM) - && !crtl->calls_eh_return) + && !crtl->calls_eh_return + && !arm_current_function_pac_enabled_p ()) { saved_regs_mask &= ~(1 << LR_REGNUM); saved_regs_mask |= (1 << PC_REGNUM); @@ -27958,6 +27995,9 @@ arm_expand_epilogue (bool really_return) } } + if (arm_current_function_pac_enabled_p ()) + emit_insn (gen_aut_nop ()); + if (!really_return) return; @@ -33059,6 +33099,22 @@ arm_fusion_enabled_p (tune_params::fuse_ops op) return current_tune->fusible_ops & op; } +/* Return TRUE if return address signing mechanism is enabled. */ +bool +arm_current_function_pac_enabled_p (void) +{ + return (aarch_ra_sign_scope == AARCH_FUNCTION_ALL + || (aarch_ra_sign_scope == AARCH_FUNCTION_NON_LEAF + && !crtl->is_leaf)); +} + +/* Return TRUE if Branch Target Identification Mechanism is enabled. */ +static bool +aarch_bti_enabled () +{ + return false; +} + /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be scheduled for speculative execution. Reject the long-running division and square-root instructions. */ diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index ff8452ea04a..5f7c40805d3 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -506,6 +506,10 @@ extern int arm_arch8_3; /* Nonzero if this chip supports the ARM Architecture 8.4 extensions. */ extern int arm_arch8_4; +/* Nonzero if this chip supports the ARM Architecture 8-M Mainline + extensions. */ +extern int arm_arch8m_main; + /* Nonzero if this chip supports the ARM Architecture 8.1-M Mainline extensions. */ extern int arm_arch8_1m_main; diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 69bf343fb0e..4c1bbcae850 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -12978,6 +12978,29 @@ (define_insn "*speculation_barrier_insn" (set_attr "length" "8")] ) +(define_insn "pac_nop" + [(set (reg:SI IP_REGNUM) + (unspec:SI [(reg:SI SP_REGNUM) (reg:SI LR_REGNUM)] + UNSPEC_PAC_NOP))] + "arm_arch8m_main" + "pac\t%|ip, %|lr, %|sp" + [(set_attr "conds" "unconditional")]) + +(define_insn "pacbti_nop" + [(set (reg:SI IP_REGNUM) + (unspec:SI [(reg:SI SP_REGNUM) (reg:SI LR_REGNUM)] + VUNSPEC_PACBTI_NOP))] + "arm_arch8m_main" + "pacbti\t%|ip, %|lr, %|sp" + [(set_attr "conds" "unconditional")]) + +(define_insn "aut_nop" + [(unspec:SI [(reg:SI IP_REGNUM) (reg:SI SP_REGNUM) (reg:SI LR_REGNUM)] + VUNSPEC_AUT_NOP)] + "arm_arch8m_main" + "aut\t%|ip, %|lr, %|sp" + [(set_attr "conds" "unconditional")]) + ;; Vector bits common to IWMMXT, Neon and MVE (include "vec-common.md") ;; Load the Intel Wireless Multimedia Extension patterns diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index 7748e784379..370f0b12da1 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -159,6 +159,7 @@ (define_c_enum "unspec" [ UNSPEC_VCDE ; Custom Datapath Extension instruction. UNSPEC_VCDEA ; Custom Datapath Extension instruction. UNSPEC_DLS ; Used for DLS (Do Loop Start), Armv8.1-M Mainline instruction + UNSPEC_PAC_NOP ; Represents PAC signing LR ]) @@ -254,6 +255,8 @@ (define_c_enum "unspecv" [ ; instruction. VUNSPEC_VLLDM ; Represent the lazy load multiple with vlldm ; instruction. + VUNSPEC_PACBTI_NOP ; Represents PAC signing LR + valid landing pad + VUNSPEC_AUT_NOP ; Represents PAC verifying LR ]) ;; Enumerators for NEON unspecs. diff --git a/gcc/testsuite/gcc.target/arm/pac-1.c b/gcc/testsuite/gcc.target/arm/pac-1.c new file mode 100644 index 00000000000..9b26f62b65f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-1.c @@ -0,0 +1,11 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-require-effective-target mbranch_protection_ok } */ +/* { dg-require-effective-target arm_pacbti_hw } */ +/* { dg-options "-march=armv8.1-m.main+pacbti+fp -mbranch-protection=pac-ret+leaf -mthumb -mfloat-abi=hard --save-temps -O0" } */ + +#include "pac.h" + +/* { dg-final { scan-assembler-times "pac\tip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-times "aut\tip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-not "\tbti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-10.c b/gcc/testsuite/gcc.target/arm/pac-10.c new file mode 100644 index 00000000000..a794195e8f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-10.c @@ -0,0 +1,10 @@ +/* Testing return address signing. */ +/* { dg-do compile } */ +/* { dg-require-effective-target mbranch_protection_ok } */ +/* { dg-options "-march=armv8.1-m.main+pacbti+fp -mbranch-protection=pac-ret -mthumb -mfloat-abi=hard --save-temps -O0" } */ + +#include "pac.h" + +/* { dg-final { scan-assembler "pac\tip, lr, sp" } } */ +/* { dg-final { scan-assembler "aut\tip, lr, sp" } } */ +/* { dg-final { scan-assembler-not "\tbti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-11.c b/gcc/testsuite/gcc.target/arm/pac-11.c new file mode 100644 index 00000000000..37ffc93b41b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-11.c @@ -0,0 +1,10 @@ +/* Testing return address signing. */ +/* { dg-do compile } */ +/* { dg-require-effective-target mbranch_protection_ok } */ +/* { dg-options "-march=armv8.1-m.main+pacbti+fp -mbranch-protection=bti+pac-ret+leaf -mthumb -mfloat-abi=hard --save-temps -O2" } */ + +#include "pac.h" + +/* { dg-final { scan-assembler-times "pacbti\tip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-times "aut\tip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-not "\tbti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-2.c b/gcc/testsuite/gcc.target/arm/pac-2.c new file mode 100644 index 00000000000..945ce938592 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-2.c @@ -0,0 +1,11 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-require-effective-target mbranch_protection_ok } */ +/* { dg-require-effective-target arm_pacbti_hw } */ +/* { dg-options "-march=armv8.1-m.main+pacbti+fp -mbranch-protection=pac-ret -mthumb -mfloat-abi=hard --save-temps -O0" } */ + +#include "pac.h" + +/* { dg-final { scan-assembler "pac\tip, lr, sp" } } */ +/* { dg-final { scan-assembler "aut\tip, lr, sp" } } */ +/* { dg-final { scan-assembler-not "\tbti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-3.c b/gcc/testsuite/gcc.target/arm/pac-3.c new file mode 100644 index 00000000000..47e290a5840 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-3.c @@ -0,0 +1,11 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-require-effective-target mbranch_protection_ok } */ +/* { dg-require-effective-target arm_pacbti_hw } */ +/* { dg-options "-march=armv8.1-m.main+pacbti+fp -mbranch-protection=bti+pac-ret+leaf -mthumb -mfloat-abi=hard --save-temps -O2" } */ + +#include "pac.h" + +/* { dg-final { scan-assembler-times "pacbti\tip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-times "aut\tip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-not "\tbti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-4.c b/gcc/testsuite/gcc.target/arm/pac-4.c new file mode 100644 index 00000000000..cf915cdba50 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-4.c @@ -0,0 +1,10 @@ +/* Testing return address signing. */ +/* { dg-do compile } */ +/* { dg-require-effective-target mbranch_protection_ok } */ +/* { dg-options "-march=armv8.1-m.main+pacbti+fp -mthumb -mfloat-abi=hard --save-temps -O2" } */ + +#include "pac.h" + +/* { dg-final { scan-assembler-not "\tbti\t" } } */ +/* { dg-final { scan-assembler-not "\tpac\t" } } */ +/* { dg-final { scan-assembler-not "\tpacbti\t" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-5.c b/gcc/testsuite/gcc.target/arm/pac-5.c new file mode 100644 index 00000000000..c70087eb6b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-5.c @@ -0,0 +1,28 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-require-effective-target mbranch_protection_ok } */ +/* { dg-require-effective-target arm_pacbti_hw } */ +/* { dg-options "-march=armv8.1-m.main+pacbti+fp -mbranch-protection=pac-ret+leaf -mthumb -mfloat-abi=hard --save-temps -O0" } */ + +#include + +int +__attribute__((noinline)) +foo1 (int a, int b) +{ + int square (int z) { return z * z; } + return square (a) + square (b); +} + +int +main (void) +{ + if (foo1 (1, 2) != 5) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler-times "pac\tip, lr, sp" 3 } } */ +/* { dg-final { scan-assembler-times "aut\tip, lr, sp" 3 } } */ +/* { dg-final { scan-assembler-not "\tbti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-6.c b/gcc/testsuite/gcc.target/arm/pac-6.c new file mode 100644 index 00000000000..c5329f0ef48 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-6.c @@ -0,0 +1,18 @@ +/* Check that GCC does .save and .cfi_offset directives with RA_AUTH_CODE pseudo hard-register. */ +/* { dg-do compile } */ +/* { dg-require-effective-target mbranch_protection_ok } */ +/* { dg-options "-march=armv8.1-m.main+fp -mbranch-protection=pac-ret+leaf -mthumb --save-temps -O0 -g" } */ + +int i; + +void foo (int); + +int bar() +{ + foo (i); + return 0; +} + +/* { dg-final { scan-assembler "pac\tip, lr, sp" } } */ +/* { dg-final { scan-assembler "aut\tip, lr, sp" } } */ +/* { dg-final { scan-assembler-not "bti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-7.c b/gcc/testsuite/gcc.target/arm/pac-7.c new file mode 100644 index 00000000000..cdaebca5cfa --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-7.c @@ -0,0 +1,32 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-require-effective-target mbranch_protection_ok } */ +/* { dg-require-effective-target arm_pacbti_hw } */ +/* { dg-options "-march=armv8.1-m.main+pacbti+fp -mbranch-protection=pac-ret+leaf -mthumb -mfloat-abi=hard --save-temps -O0" } */ + +#include + +int +__attribute__((noinline)) +foo1 (int a, int b) +{ + int x = 4; + int foo2 (int a, int b) + { + return a + b + x; + } + return foo2 (a, b); +} + +int +main (void) +{ + if (foo1 (1, 2) != 7) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler-times "pac\tip, lr, sp" 3 } } */ +/* { dg-final { scan-assembler-times "aut\tip, lr, sp" 3 } } */ +/* { dg-final { scan-assembler-not "\tbti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-8.c b/gcc/testsuite/gcc.target/arm/pac-8.c new file mode 100644 index 00000000000..3f37dcfa5c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-8.c @@ -0,0 +1,34 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-require-effective-target mbranch_protection_ok } */ +/* { dg-require-effective-target arm_pacbti_hw } */ +/* { dg-options "-march=armv8.1-m.main+pacbti+fp -mbranch-protection=pac-ret+leaf -mthumb -mfloat-abi=hard --save-temps -O0" } */ + +#include +#include + +int acc (int n, ...) +{ + int sum = 0; + va_list ptr; + + va_start (ptr, n); + + for (int i = 0; i < n; i++) + sum += va_arg (ptr, int); + va_end (ptr); + + return sum; +} + +int main() +{ + if (acc (3, 1, 2, 3) != 6) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler-times "pac\tip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-times "aut\tip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-not "\tbti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-9.c b/gcc/testsuite/gcc.target/arm/pac-9.c new file mode 100644 index 00000000000..ee2fad290b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-9.c @@ -0,0 +1,11 @@ +/* Testing return address signing. */ +/* { dg-do compile } */ +/* { dg-require-effective-target mbranch_protection_ok } */ +/* { dg-options "-march=armv8.1-m.main+pacbti+fp -mbranch-protection=pac-ret+leaf -mthumb -mfloat-abi=hard --save-temps -O0" } */ + +#include "pac.h" + +/* { dg-final { scan-assembler-times "pac\tip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-times "aut\tip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-not "\tbti" } } */ + diff --git a/gcc/testsuite/gcc.target/arm/pac.h b/gcc/testsuite/gcc.target/arm/pac.h new file mode 100644 index 00000000000..7355e6b2954 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac.h @@ -0,0 +1,17 @@ +#include + +int +__attribute__((noinline)) +foo1 (int a, int b) +{ + return a + b; +} + +int +main (void) +{ + if (foo1 (1, 2) != 3) + abort (); + + return 0; +} -- 2.25.1 --=-=-=--