From: Andrea Corallo <andrea.corallo@arm.com>
To: Andrea Corallo via Gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>, nd <nd@arm.com>
Subject: [PATCH 11/15] aarch64: Make bti pass generic so it can be used by the arm backend
Date: Fri, 12 Aug 2022 17:40:18 +0200 [thread overview]
Message-ID: <gkr8rntbhct.fsf@arm.com> (raw)
In-Reply-To: <gkrk07dczbq.fsf@arm.com> (Andrea Corallo via Gcc-patches's message of "Fri, 12 Aug 2022 16:26:49 +0200")
[-- Attachment #1: Type: text/plain, Size: 1088 bytes --]
Hi all,
this patch splits and restructures the aarch64 bti pass code in order
to have it usable by the arm backend as well. These changes have no
functional impact.
The original patch was approved here:
<https://gcc.gnu.org/pipermail/gcc-patches/2022-May/594172.html>.
After that Richard E. noted that was better to move the new pass
definition for arm in the following patch and so I did.
Best Regards
Andrea
gcc/Changelog
* config.gcc (aarch64*-*-*): Rename 'aarch64-bti-insert.o' into
'aarch-bti-insert.o'.
* config/aarch64/aarch64-protos.h: Remove 'aarch64_bti_enabled'
proto.
* config/aarch64/aarch64.cc (aarch_bti_enabled): Rename.
(aarch_bti_j_insn_p, aarch_pac_insn_p): New functions.
(aarch64_output_mi_thunk)
(aarch64_print_patchable_function_entry)
(aarch64_file_end_indicate_exec_stack): Update renamed function
calls to renamed functions.
* config/aarch64/t-aarch64 (aarch-bti-insert.o): Update target.
* config/arm/aarch-bti-insert.cc: New file including and
generalizing code from aarch64-bti-insert.cc.
* config/arm/aarch-common-protos.h: Update.
[-- Attachment #2: 11-15.patch --]
[-- Type: text/plain, Size: 10995 bytes --]
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 7b58e1314ff..2021bdf9d2f 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -329,7 +329,7 @@ aarch64*-*-*)
c_target_objs="aarch64-c.o"
cxx_target_objs="aarch64-c.o"
d_target_objs="aarch64-d.o"
- extra_objs="aarch64-builtins.o aarch-common.o aarch64-sve-builtins.o aarch64-sve-builtins-shapes.o aarch64-sve-builtins-base.o aarch64-sve-builtins-sve2.o cortex-a57-fma-steering.o aarch64-speculation.o falkor-tag-collision-avoidance.o aarch64-bti-insert.o aarch64-cc-fusion.o"
+ extra_objs="aarch64-builtins.o aarch-common.o aarch64-sve-builtins.o aarch64-sve-builtins-shapes.o aarch64-sve-builtins-base.o aarch64-sve-builtins-sve2.o cortex-a57-fma-steering.o aarch64-speculation.o falkor-tag-collision-avoidance.o aarch-bti-insert.o aarch64-cc-fusion.o"
target_gtfiles="\$(srcdir)/config/aarch64/aarch64-builtins.cc \$(srcdir)/config/aarch64/aarch64-sve-builtins.h \$(srcdir)/config/aarch64/aarch64-sve-builtins.cc"
target_has_targetm_common=yes
;;
diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
index b0c5a4fd6b6..a9aad3abdc2 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -179,7 +179,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
aarch64_def_or_undef (TARGET_RNG, "__ARM_FEATURE_RNG", pfile);
aarch64_def_or_undef (TARGET_MEMTAG, "__ARM_FEATURE_MEMORY_TAGGING", pfile);
- aarch64_def_or_undef (aarch64_bti_enabled (),
+ aarch64_def_or_undef (aarch_bti_enabled (),
"__ARM_FEATURE_BTI_DEFAULT", pfile);
cpp_undef (pfile, "__ARM_FEATURE_PAC_DEFAULT");
diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index fe2180e95ea..9fdf7f9cc9c 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -891,7 +891,6 @@ void aarch64_register_pragmas (void);
void aarch64_relayout_simd_types (void);
void aarch64_reset_previous_fndecl (void);
bool aarch64_return_address_signing_enabled (void);
-bool aarch64_bti_enabled (void);
void aarch64_save_restore_target_globals (tree);
void aarch64_addti_scratch_regs (rtx, rtx, rtx *,
rtx *, rtx *,
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index eec743024c1..2f67f3872f6 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -8534,11 +8534,61 @@ aarch64_return_address_signing_enabled (void)
/* Return TRUE if Branch Target Identification Mechanism is enabled. */
bool
-aarch64_bti_enabled (void)
+aarch_bti_enabled (void)
{
return (aarch_enable_bti == 1);
}
+/* Check if INSN is a BTI J insn. */
+bool
+aarch_bti_j_insn_p (rtx_insn *insn)
+{
+ if (!insn || !INSN_P (insn))
+ return false;
+
+ rtx pat = PATTERN (insn);
+ return GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_BTI_J;
+}
+
+/* Check if X (or any sub-rtx of X) is a PACIASP/PACIBSP instruction. */
+bool
+aarch_pac_insn_p (rtx x)
+{
+ if (!INSN_P (x))
+ return false;
+
+ subrtx_var_iterator::array_type array;
+ FOR_EACH_SUBRTX_VAR (iter, array, PATTERN (x), ALL)
+ {
+ rtx sub = *iter;
+ if (sub && GET_CODE (sub) == UNSPEC)
+ {
+ int unspec_val = XINT (sub, 1);
+ switch (unspec_val)
+ {
+ case UNSPEC_PACIASP:
+ case UNSPEC_PACIBSP:
+ return true;
+
+ default:
+ return false;
+ }
+ iter.skip_subrtxes ();
+ }
+ }
+ return false;
+}
+
+rtx aarch_gen_bti_c (void)
+{
+ return gen_bti_c ();
+}
+
+rtx aarch_gen_bti_j (void)
+{
+ return gen_bti_j ();
+}
+
/* The caller is going to use ST1D or LD1D to save or restore an SVE
register in mode MODE at BASE_RTX + OFFSET, where OFFSET is in
the range [1, 16] * GET_MODE_SIZE (MODE). Prepare for this by:
@@ -9918,7 +9968,7 @@ aarch64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
rtx_insn *insn;
const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk));
- if (aarch64_bti_enabled ())
+ if (aarch_bti_enabled ())
emit_insn (gen_bti_c());
reload_completed = 1;
@@ -22360,7 +22410,7 @@ aarch64_print_patchable_function_entry (FILE *file,
bool record_p)
{
if (cfun->machine->label_is_assembled
- && aarch64_bti_enabled ()
+ && aarch_bti_enabled ()
&& !cgraph_node::get (cfun->decl)->only_called_directly_p ())
{
/* Remove the BTI that follows the patch area and insert a new BTI
@@ -26689,7 +26739,7 @@ aarch64_file_end_indicate_exec_stack ()
file_end_indicate_exec_stack ();
unsigned feature_1_and = 0;
- if (aarch64_bti_enabled ())
+ if (aarch_bti_enabled ())
feature_1_and |= GNU_PROPERTY_AARCH64_FEATURE_1_BTI;
if (aarch_ra_sign_scope != AARCH_FUNCTION_NONE)
diff --git a/gcc/config/aarch64/t-aarch64 b/gcc/config/aarch64/t-aarch64
index 75b463d2f03..eb6ad3db955 100644
--- a/gcc/config/aarch64/t-aarch64
+++ b/gcc/config/aarch64/t-aarch64
@@ -149,14 +149,14 @@ falkor-tag-collision-avoidance.o: \
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
$(srcdir)/config/aarch64/falkor-tag-collision-avoidance.cc
-aarch64-bti-insert.o: $(srcdir)/config/aarch64/aarch64-bti-insert.cc \
+aarch-bti-insert.o: $(srcdir)/config/arm/aarch-bti-insert.cc \
$(CONFIG_H) $(SYSTEM_H) $(TM_H) $(REGS_H) insn-config.h $(RTL_BASE_H) \
dominance.h cfg.h cfganal.h $(BASIC_BLOCK_H) $(INSN_ATTR_H) $(RECOG_H) \
output.h hash-map.h $(DF_H) $(OBSTACK_H) $(TARGET_H) $(RTL_H) \
$(CONTEXT_H) $(TREE_PASS_H) regrename.h \
$(srcdir)/config/aarch64/aarch64-protos.h
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
- $(srcdir)/config/aarch64/aarch64-bti-insert.cc
+ $(srcdir)/config/arm/aarch-bti-insert.cc
aarch64-cc-fusion.o: $(srcdir)/config/aarch64/aarch64-cc-fusion.cc \
$(CONFIG_H) $(SYSTEM_H) $(CORETYPES_H) $(BACKEND_H) $(RTL_H) $(DF_H) \
diff --git a/gcc/config/aarch64/aarch64-bti-insert.cc b/gcc/config/arm/aarch-bti-insert.cc
similarity index 80%
rename from gcc/config/aarch64/aarch64-bti-insert.cc
rename to gcc/config/arm/aarch-bti-insert.cc
index 7caed310bbc..2d1d2e334a9 100644
--- a/gcc/config/aarch64/aarch64-bti-insert.cc
+++ b/gcc/config/arm/aarch-bti-insert.cc
@@ -42,10 +42,11 @@
#include "tree-pass.h"
#include "cgraph.h"
-/* This pass enables the support for Branch Target Identification Mechanism
- for AArch64. This is a new security feature introduced in ARMv8.5-A
- archtitecture. A BTI instruction is used to guard against the execution
- of instructions which are not the intended target of an indirect branch.
+/* This pass enables the support for Branch Target Identification Mechanism for
+ Arm/AArch64. This is a security feature introduced in ARMv8.5-A
+ architecture and ARMv8.1-M. A BTI instruction is used to guard against the
+ execution of instructions which are not the intended target of an indirect
+ branch.
Outside of a guarded memory region, a BTI instruction executes as a NOP.
Within a guarded memory region any target of an indirect branch must be
@@ -53,7 +54,8 @@
branch is triggered in a non-guarded memory region). An incompatibility
generates a Branch Target Exception.
- The compatibility of the BTI instruction is as follows:
+ The compatibility of the BTI instruction is as follows (AArch64
+ examples):
BTI j : Can be a target of any indirect jump (BR Xn).
BTI c : Can be a target of any indirect call (BLR Xn and BR X16/X17).
BTI jc: Can be a target of any indirect call or indirect jump.
@@ -90,47 +92,6 @@ const pass_data pass_data_insert_bti =
0, /* todo_flags_finish. */
};
-/* Check if X (or any sub-rtx of X) is a PACIASP/PACIBSP instruction. */
-static bool
-aarch64_pac_insn_p (rtx x)
-{
- if (!INSN_P (x))
- return false;
-
- subrtx_var_iterator::array_type array;
- FOR_EACH_SUBRTX_VAR (iter, array, PATTERN (x), ALL)
- {
- rtx sub = *iter;
- if (sub && GET_CODE (sub) == UNSPEC)
- {
- int unspec_val = XINT (sub, 1);
- switch (unspec_val)
- {
- case UNSPEC_PACIASP:
- /* fall-through. */
- case UNSPEC_PACIBSP:
- return true;
-
- default:
- return false;
- }
- iter.skip_subrtxes ();
- }
- }
- return false;
-}
-
-/* Check if INSN is a BTI J insn. */
-static bool
-aarch64_bti_j_insn_p (rtx_insn *insn)
-{
- if (!insn || !INSN_P (insn))
- return false;
-
- rtx pat = PATTERN (insn);
- return GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_BTI_J;
-}
-
/* Insert the BTI instruction. */
/* This is implemented as a late RTL pass that runs before branch
shortening and does the following. */
@@ -155,7 +116,7 @@ rest_of_insert_bti (void)
&& (LABEL_PRESERVE_P (insn)
|| bb->flags & BB_NON_LOCAL_GOTO_TARGET))
{
- bti_insn = gen_bti_j ();
+ bti_insn = aarch_gen_bti_j ();
emit_insn_after (bti_insn, insn);
continue;
}
@@ -177,10 +138,10 @@ rest_of_insert_bti (void)
{
label = as_a <rtx_insn *> (XEXP (RTVEC_ELT (vec, j), 0));
rtx_insn *next = next_nonnote_nondebug_insn (label);
- if (aarch64_bti_j_insn_p (next))
+ if (aarch_bti_j_insn_p (next))
continue;
- bti_insn = gen_bti_j ();
+ bti_insn = aarch_gen_bti_j ();
emit_insn_after (bti_insn, label);
}
}
@@ -191,7 +152,7 @@ rest_of_insert_bti (void)
will return. */
if (CALL_P (insn) && (find_reg_note (insn, REG_SETJMP, NULL)))
{
- bti_insn = gen_bti_j ();
+ bti_insn = aarch_gen_bti_j ();
emit_insn_after (bti_insn, insn);
continue;
}
@@ -207,9 +168,9 @@ rest_of_insert_bti (void)
{
bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb;
insn = BB_HEAD (bb);
- if (!aarch64_pac_insn_p (get_first_nonnote_insn ()))
+ if (!aarch_pac_insn_p (get_first_nonnote_insn ()))
{
- bti_insn = gen_bti_c ();
+ bti_insn = aarch_gen_bti_c ();
emit_insn_before (bti_insn, insn);
}
}
@@ -229,7 +190,7 @@ public:
/* opt_pass methods: */
virtual bool gate (function *)
{
- return aarch64_bti_enabled ();
+ return aarch_bti_enabled ();
}
virtual unsigned int execute (function *)
diff --git a/gcc/config/arm/aarch-common-protos.h b/gcc/config/arm/aarch-common-protos.h
index 17a369f7e99..374982752ad 100644
--- a/gcc/config/arm/aarch-common-protos.h
+++ b/gcc/config/arm/aarch-common-protos.h
@@ -42,6 +42,11 @@ extern int arm_no_early_alu_shift_value_dep (rtx, rtx);
extern int arm_no_early_mul_dep (rtx, rtx);
extern int arm_no_early_store_addr_dep (rtx, rtx);
extern bool arm_rtx_shift_left_p (rtx);
+extern bool aarch_bti_enabled (void);
+extern bool aarch_bti_j_insn_p (rtx_insn *);
+extern bool aarch_pac_insn_p (rtx);
+extern rtx aarch_gen_bti_c (void);
+extern rtx aarch_gen_bti_j (void);
/* RTX cost table definitions. These are used when tuning for speed rather
than for size and should reflect the _additional_ cost over the cost
next prev parent reply other threads:[~2022-08-12 15:40 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-12 14:26 [PATCH 0/15] arm: Enables return address verification and branch target identification on Cortex-M Andrea Corallo
2022-08-12 15:14 ` [PATCH 1/15] arm: Make mbranch-protection opts parsing common to AArch32/64 Andrea Corallo
2022-12-22 17:04 ` [PATCH 1/15 V2] " Andrea Corallo
2023-01-11 10:48 ` Richard Earnshaw
2022-08-12 15:15 ` [PATCH 2/15] arm: Add Armv8.1-M Mainline target feature +pacbti Andrea Corallo
2022-08-12 15:21 ` [PATCH 3/15] arm: Add option -mbranch-protection Andrea Corallo
2022-08-12 15:22 ` [PATCH 4/15] arm: Add testsuite library support for PACBTI target Andrea Corallo
2022-08-12 15:26 ` [PATCH 5/15] arm: Implement target feature macros for PACBTI Andrea Corallo
2022-08-12 15:29 ` [PATCH 6/15] arm: Add pointer authentication for stack-unwinding runtime Andrea Corallo
2022-08-12 15:30 ` [PATCH 7/15] arm: Emit build attributes for PACBTI target feature Andrea Corallo
2022-09-05 16:53 ` Andrea Corallo
2022-10-20 14:47 ` Kyrylo Tkachov
2022-10-20 15:15 ` Richard Earnshaw
2022-10-21 12:19 ` Richard Earnshaw
2022-08-12 15:33 ` [PATCH 8/15] arm: Introduce multilibs " Andrea Corallo
2022-08-12 15:34 ` [PATCH 9/15] arm: Set again stack pointer as CFA reg when popping if necessary Andrea Corallo
2022-09-05 16:52 ` Andrea Corallo
2022-09-27 9:03 ` Kyrylo Tkachov
2022-09-27 10:05 ` Andrea Corallo
2022-09-27 15:24 ` Kyrylo Tkachov
2022-10-21 12:30 ` Richard Earnshaw
2022-10-26 8:49 ` Andrea Corallo
2022-11-08 14:57 ` Richard Earnshaw
2023-01-09 14:58 ` Andrea Corallo
2023-01-09 15:57 ` Richard Earnshaw
2023-01-09 16:48 ` Richard Earnshaw
2023-01-09 17:22 ` Richard Earnshaw
2023-01-11 9:55 ` Andrea Corallo
2022-08-12 15:36 ` [PATCH 10/15] arm: Implement cortex-M return signing address codegen Andrea Corallo
2022-09-05 16:55 ` Andrea Corallo
2022-09-14 14:20 ` [PATCH 10/15 V2] " Andrea Corallo
2022-10-21 12:58 ` Richard Earnshaw
2022-10-26 15:48 ` Andrea Corallo
2022-10-28 16:34 ` [PATCH 10/15 V3] " Andrea Corallo
2022-11-07 8:57 ` [PATCH 10/15 V4] " Andrea Corallo
2022-12-05 16:38 ` Richard Earnshaw
2022-12-09 14:16 ` [PATCH 10/15 V5] " Andrea Corallo
2022-12-12 10:53 ` Richard Earnshaw
2022-12-14 16:35 ` [PATCH 10/15 V6] " Andrea Corallo
2022-12-14 16:45 ` Richard Earnshaw
2023-01-11 9:58 ` [PATCH 10/15 V7] " Andrea Corallo
2023-01-11 10:39 ` Richard Earnshaw
2022-08-12 15:40 ` Andrea Corallo [this message]
2022-09-05 16:56 ` [PATCH 11/15] aarch64: Make bti pass generic so it can be used by the arm backend Andrea Corallo
2022-09-27 9:10 ` Kyrylo Tkachov
2022-08-12 15:41 ` [PATCH 12/15] arm: implement bti injection Andrea Corallo
2022-09-05 16:56 ` Andrea Corallo
2022-09-27 9:18 ` Kyrylo Tkachov
2022-09-29 15:45 ` [PATCH 12/15 V2] " Andrea Corallo
2022-10-20 14:56 ` Kyrylo Tkachov
2022-10-28 16:40 ` [PATCH 12/15 V3] " Andrea Corallo
2022-12-05 17:02 ` Richard Earnshaw
2022-12-14 16:40 ` [PATCH 12/15 V4] " Andrea Corallo
2022-12-14 17:00 ` Richard Earnshaw
2022-12-14 17:03 ` Richard Earnshaw
2022-12-22 17:13 ` [PATCH 12/15 V5] " Andrea Corallo
2023-01-11 15:08 ` Richard Earnshaw
2022-08-12 16:44 ` [PATCH 0/15] arm: Enables return address verification and branch target identification on Cortex-M Andrea Corallo
2022-08-12 17:10 ` [PATCH 13/15] arm: Add pacbti related multilib support for armv8.1-m.main Srinath Parvathaneni
2022-10-21 13:00 ` Richard Earnshaw
2022-09-21 8:07 ` [PING][PATCH 0/15] arm: Enables return address verification and branch target identification on Cortex-M Andrea Corallo
2022-10-21 13:01 ` Richard Earnshaw
2022-10-21 13:32 ` Andrea Corallo
2022-12-05 14:10 ` Andrea Corallo
2022-12-05 14:19 ` Kyrylo Tkachov
2023-01-23 10:50 ` [PATCH " Andrea Corallo
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