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Wed, 26 Oct 2022 15:48:00 +0000 From: Andrea Corallo To: Richard Earnshaw CC: Andrea Corallo via Gcc-patches , "Richard Earnshaw" , nd Subject: Re: [PATCH 10/15 V2] arm: Implement cortex-M return signing address codegen In-Reply-To: (Richard Earnshaw's message of "Fri, 21 Oct 2022 13:58:13 +0100") References: Date: Wed, 26 Oct 2022 17:48:00 +0200 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT006:EE_|AS8PR08MB9815:EE_|DBAEUR03FT031:EE_|AS8PR08MB8086:EE_ X-MS-Office365-Filtering-Correlation-Id: 10440a5d-bfa3-45e9-6091-08dab7697bc2 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: c8MgvQ57mhCzfR9g1v6VlD6SatPSqmZCukUz6Q1Mh7I2Wx4f3gmjmnPXZLo478fm/YOyk/UcjVFnazOj3MnS3cnLPFffOZd1XvxXmu6uqXyOt3hR0L7Q9mnOrebTFv6Co19KcmJklU6PAPGNbGHV1KL64ck+aLWfYXKvXQhivo7kArHoNiBBh1srHjWCPrn4Uu91Hx4XMkLp+7lorOKmR8nkZtBDgqmc+TNioD0S/WCH8CR3OCmv46fRTpBYsiEqoVW+jdxQXNjCmUumjQAAhBN+T4ziAkZZMh3818oAOVsRw3iO2D5D46WTe8h9jQGj8cLgscM2Rq2G58T8LvBj5d54Qunf/lvqy1Gtm9eFVzOeZIQDLZMUcol4dGSEBAZjQA1cM9WNfBoQgYjmLZ/a6JUqAQure50iiwMTuIFN7STNLPvCuS/1G9YqlwKV+y51NyBbUOAfq0ENtr3uX40bpQLVQAP1O90IB6iuu+VdSUeU7li/B1q/ddGjrInrPM24XGIs0VFaJDh6HuYrb7IJ7KSZio/M78RpbVdG33+x7FqgLGAWiDdObABnMr3Jz1IHezc7JKx/2StQ6wW3gNYNK44CdRX9mgfQP617qtEPgJ0Xs4T4/qkGOjSk7mRNSoirtHKweZ1kNLRh5KGPeb/8nPDZncfSHTrqF/fhdjOz8zZByX2n0o8N6/GAWPuwc2C/y3dNFWoSvwxkewDfeJDQKGC4FnYpv9fRrn/4frAfFRHY5fPFDvR/V7iT5MtKclzaIeoONlF8n5NFXDbG3c8u9beoJ/5K/3CvUp+7vd21ANNjxZGyubZlmfzy9m6p3lTti0SXrEpL03B5let8qLlAZNFjINz7Kyd6pIOipX07C+ymPJa64JcK2gJYlQk6jIIo X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(396003)(136003)(346002)(39860400002)(451199015)(46966006)(36840700001)(40470700004)(82310400005)(36756003)(82740400003)(84970400001)(83380400001)(426003)(41300700001)(8936002)(4326008)(6862004)(2906002)(40480700001)(8676002)(54906003)(70586007)(70206006)(316002)(86362001)(186003)(5660300002)(2616005)(53546011)(356005)(47076005)(44832011)(81166007)(336012)(40460700003)(26005)(478600001)(36860700001)(36900700001);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Oct 2022 15:48:10.1975 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 10440a5d-bfa3-45e9-6091-08dab7697bc2 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT031.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB8086 X-Spam-Status: No, score=-6.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,KAM_DMARC_NONE,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Richard Earnshaw writes: > On 14/09/2022 15:20, Andrea Corallo via Gcc-patches wrote: >> Hi all, >> >> this patch enables address return signature and verification based on >> Armv8.1-M Pointer Authentication [1]. >> >> To sign the return address, we use the PAC R12, LR, SP instruction >> upon function entry. This is signing LR using SP and storing the >> result in R12. R12 will be pushed into the stack. >> >> During function epilogue R12 will be popped and AUT R12, LR, SP will >> be used to verify that the content of LR is still valid before return. >> >> Here an example of PAC instrumented function prologue and epilogue: >> >> void foo (void); >> >> int main() >> { >> foo (); >> return 0; >> } >> >> Compiled with '-march=armv8.1-m.main -mbranch-protection=pac-ret >> -mthumb' translates into: >> >> main: >> pac ip, lr, sp >> push {r3, r7, ip, lr} >> add r7, sp, #0 >> bl foo >> movs r3, #0 >> mov r0, r3 >> pop {r3, r7, ip, lr} >> aut ip, lr, sp >> bx lr >> >> The patch also takes care of generating a PACBTI instruction in place >> of the sequence BTI+PAC when Branch Target Identification is enabled >> contextually. >> >> Ex. the previous example compiled with '-march=armv8.1-m.main >> -mbranch-protection=pac-ret+bti -mthumb' translates into: >> >> main: >> pacbti ip, lr, sp >> push {r3, r7, ip, lr} >> add r7, sp, #0 >> bl foo >> movs r3, #0 >> mov r0, r3 >> pop {r3, r7, ip, lr} >> aut ip, lr, sp >> bx lr >> >> As part of previous upstream suggestions a test for varargs has been >> added and '-mtpcs-frame' is deemed being incompatible with this return >> signing address feature being introduced. >> >> [1] >> >> gcc/Changelog >> >> 2021-11-03 Andrea Corallo >> >> * config/arm/arm.c: (arm_compute_frame_layout) >> (arm_expand_prologue, thumb2_expand_return, arm_expand_epilogue) >> (arm_conditional_register_usage): Update for pac codegen. >> (arm_current_function_pac_enabled_p): New function. >> * config/arm/arm.md (pac_ip_lr_sp, pacbti_ip_lr_sp, aut_ip_lr_sp): >> Add new patterns. >> * config/arm/unspecs.md (UNSPEC_PAC_IP_LR_SP) >> (UNSPEC_PACBTI_IP_LR_SP, UNSPEC_AUT_IP_LR_SP): Add unspecs. >> >> gcc/testsuite/Changelog >> >> 2021-11-03 Andrea Corallo >> >> * gcc.target/arm/pac.h : New file. >> * gcc.target/arm/pac-1.c : New test case. >> * gcc.target/arm/pac-2.c : Likewise. >> * gcc.target/arm/pac-3.c : Likewise. >> * gcc.target/arm/pac-4.c : Likewise. >> * gcc.target/arm/pac-5.c : Likewise. >> * gcc.target/arm/pac-6.c : Likewise. >> * gcc.target/arm/pac-7.c : Likewise. >> * gcc.target/arm/pac-8.c : Likewise. >> > > + if (arm_current_function_pac_enabled_p () && !(arm_arch7 && > arm_arch_cmse)) > + error ("This architecture does not support branch protection > instructions"); > > This test feels wrong. What does having cmse give us? I suspect you > want a test that ensures we have at least v8-m.main so that the NOP > instructions are correctly defined as NOPs (or, in this case, PACBTI > instructions) rather than unpredictable; but if that's the case then I > think you really want to write the test that way here (perhaps in a > macro) and then move this test into that so that it becomes > self-documenting - but don't we have a v8-m.main test anyway? Yep > + if (arm_current_function_pac_enabled_p ()) > + { > + gcc_assert (!(saved_regs_mask & (1 << PC_REGNUM))); > + arm_emit_multi_reg_pop (saved_regs_mask); > + emit_insn (gen_aut_nop ()); > + emit_jump_insn (simple_return_rtx); > + } > > The assert is using indents that are just spaces, but the other lines > use tabs. Please use tabs everywhere rather than mixing like this. Ack. > +/* Return TRUE if return address signing mechanism is enabled. */ > +bool > +arm_current_function_pac_enabled_p (void) > +{ > + return aarch_ra_sign_scope == AARCH_FUNCTION_ALL > + || (aarch_ra_sign_scope == AARCH_FUNCTION_NON_LEAF > + && !crtl->is_leaf); > +} > > This is a case where you should use parenthesis around the expression so > that the continuation lines are correctly indented. Ack. > @@ -11518,7 +11518,7 @@ (define_expand "prologue" > arm_expand_prologue (); > else > thumb1_expand_prologue (); > - DONE; > + DONE; > " > ) > > Although this is a trivial cleanup, it has nothing to do with this > patch. Please remove. Okay. > + "arm_arch7 && arm_arch_cmse" > > See my comments earlier about this test; the same applies here. > > + (unspec:SI [(reg:SI SP_REGNUM) (reg:SI LR_REGNUM)] > + UNSPEC_PAC_NOP))] > + > Again you have a mix of lines indented with tabs and lines indented with > just spaces. Similarly with pacbti_nop and aut_nop. > > Do you have a test for the nested functions case (I can't see it, but > perhaps I've missed it somewhere)? We have gcc/testsuite/gcc.target/arm/pac-7.c added by this patch. > R. Andrea