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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by AM7EUR03FT054.mail.protection.outlook.com (100.127.140.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5901.14 via Frontend Transport; Tue, 6 Dec 2022 17:19:36 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX04.Arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Tue, 6 Dec 2022 17:19:34 +0000 Received: from e124257 (10.34.105.24) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16 via Frontend Transport; Tue, 6 Dec 2022 17:19:33 +0000 From: Andrea Corallo To: Richard Earnshaw CC: Andrea Corallo via Gcc-patches , "Richard Earnshaw" , nd Subject: Re: [PATCH 10/15 V4] arm: Implement cortex-M return signing address codegen References: <4917eabd-7b0b-a402-3680-f5591a7bb039@foss.arm.com> Date: Tue, 6 Dec 2022 18:19:33 +0100 In-Reply-To: <4917eabd-7b0b-a402-3680-f5591a7bb039@foss.arm.com> (Richard Earnshaw's message of "Tue, 6 Dec 2022 16:24:21 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2.50 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT054:EE_|AM8PR08MB6531:EE_|AM7EUR03FT006:EE_|AS8PR08MB9429:EE_ X-MS-Office365-Filtering-Correlation-Id: 4bc485f8-0ad5-40c8-f319-08dad7ae1374 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2022 17:19:47.6434 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4bc485f8-0ad5-40c8-f319-08dad7ae1374 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT006.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB9429 X-Spam-Status: No, score=-5.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,KAM_DMARC_NONE,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Richard Earnshaw writes: > On 06/12/2022 15:46, Andrea Corallo wrote: >> Hi Richard, >> thanks for reviewing. >> Just one clarification before I complete the respin of this patch. >> Richard Earnshaw writes: >> [...] >> >>> Also, I think (out of an abundance of caution) we really need a >>> scheduling barrier placed before calls to gen_aut_nop() pattern is >>> emitted, to ensure that the scheduler never tries to move this >>> instruction away from the position we place it. Use gen_blockage() >>> for that (see TARGET_SCHED_PROLOG). Alternatively, we could make the >>> UNSPEC_PAC_NOP an unspec_volatile, which has the same effect (IIRC) >>> without needing an additional insn - if you use this approach, then >>> please make sure this is explained in a comment. >>> >>> +(define_insn "pacbti_nop" >>> + [(set (reg:SI IP_REGNUM) >>> + (unspec:SI [(reg:SI SP_REGNUM) (reg:SI LR_REGNUM)] >>> + UNSPEC_PACBTI_NOP))] >>> + "arm_arch8m_main" >>> + "pacbti\t%|ip, %|lr, %|sp" >>> + [(set_attr "conds" "unconditional")]) >>> >>> The additional side-effect of this being a BTI landing pad means that >>> we mustn't move any other instruction before it. So I think this >>> needs to be an unspec_volatile as well. >> IIUC from this we want to make all the three (UNSPEC_PAC_NOP, >> UNSPEC_PACBTI_NOP, UNSPEC_AUT_NOP) unspec volatile, correct? > > UNSPEC_PAC_NOP doesn't need to be volatile. The register constraints > will be enough to ensure it is run before any instruction that > consumes the result it produces. > > UNSPEC_PAC_BTI_NOP needs to be volatile, as it's essential that when > we have an instruction (for example ldr r3, [r3]) early in the program > that doesn't interact with the prologue then it cannot be migrated > before the BTI as the BTI is a landing pad and must be the first > instruction in the function. This is why UNSPEC_BTI_NOP is volatile. > > UNSPEC_AUT_NOP must be volatile because we want to ensure that no > instruction is moved after this one and before the return as that > might expose a ROP gadget to hackers. > > R. Understood now, thanks. Andrea