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dkim=none (message not signed) header.d=none;arm.com; dmarc=none action=none header.from=arm.com; Received: from DB7PR08MB3594.eurprd08.prod.outlook.com (2603:10a6:10:4e::11) by DB6PR0802MB2165.eurprd08.prod.outlook.com (2603:10a6:4:86::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3195.25; Wed, 22 Jul 2020 13:53:37 +0000 Received: from DB7PR08MB3594.eurprd08.prod.outlook.com ([fe80::9f3:461:834d:7ca]) by DB7PR08MB3594.eurprd08.prod.outlook.com ([fe80::9f3:461:834d:7ca%7]) with mapi id 15.20.3195.026; Wed, 22 Jul 2020 13:53:37 +0000 From: Andrea Corallo To: Andrew Pinski Cc: GCC Patches , nd , Richard Earnshaw Subject: Re: [PATCH 2/2] Aarch64: Add branch diluter pass References: Date: Wed, 22 Jul 2020 15:53:34 +0200 In-Reply-To: (Andrew Pinski's message of "Wed, 22 Jul 2020 03:39:33 -0700") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.0.50 (gnu/linux) Content-Type: text/plain X-ClientProxiedBy: LO2P265CA0159.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:9::27) To DB7PR08MB3594.eurprd08.prod.outlook.com (2603:10a6:10:4e::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from e112547 (217.140.99.251) by LO2P265CA0159.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:9::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3216.23 via Frontend Transport; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT052.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR0802MB2289 X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, MSGID_FROM_MTA_HEADER, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 22 Jul 2020 13:53:49 -0000 Hi Andrew, thanks for reviewing I'll work on your comments. Just replying to the high level questions. Andrew Pinski writes: > On Wed, Jul 22, 2020 at 3:10 AM Andrea Corallo wrote: >> >> Hi all, >> >> this second patch implements the AArch64 specific back-end pass >> 'branch-dilution' controllable by the followings command line options: >> >> -mbranch-dilution >> >> --param=aarch64-branch-dilution-granularity={num} >> >> --param=aarch64-branch-dilution-max-branches={num} >> >> Some cores known to be able to benefit from this pass have been given >> default tuning values for their granularity and max-branches. Each >> affected core has a very specific granule size and associated max-branch >> limit. This is a microarchitecture specific optimization. Typical >> usage should be -mbranch-dilution with a specified -mcpu. Cores with a >> granularity tuned to 0 will be ignored. Options are provided for >> experimentation. > > Can you give a simple example of what this patch does? Sure, this pass simply moves a sliding window over the insns trying to make sure that we never have more then 'max_branch' branches for every 'granule_size' insns. If too many branches are detected nops are added where considered less armful to correct that. There are obviously many scenarios where the compiler can generate a branch dense pieces of code but say we have the equivalent of: ==== .L389: bl foo b .L43 .L388: bl foo b .L42 .L387: bl foo b .L41 .L386: bl foo b .L40 ==== Assuming granule size 4 and max branches 2 this will be transformed in the equivalent of: ==== .L389: bl foo b .L43 nop nop .L388: bl foo b .L42 nop nop .L387: bl foo b .L41 nop nop .L386: bl foo b .L40 nop nop ==== > Also your testcases seem too sensitive to other optimizations which > could happen. E.g. the call to "branch (i)" could be pulled out of > the switch statement. Or even the "*i += N;" could be moved to one > Basic block and the switch becomes just one if statement. > >> Observed performance improvements on Neoverse N1 SPEC CPU 2006 where >> up to ~+3% (xalancbmk) and ~+1.5% (sjeng). Average code size increase >> for all the testsuite proved to be ~0.4%. > > Also does this improve any non-SPEC benchmarks or has it only been > benchmarked with SPEC? So far I tried it only on SPEC 2006. The transformation is not benchmark specific tho, other code may benefit from it. Thanks Andrea