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From: Andrea Corallo <andrea.corallo@arm.com>
To: Segher Boessenkool <segher@kernel.crashing.org>
Cc: Andrew Pinski <pinskia@gmail.com>,
	 Richard Earnshaw <richard.earnshaw@arm.com>,  nd <nd@arm.com>,
	 GCC Patches <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH 2/2] Aarch64: Add branch diluter pass
Date: Fri, 24 Jul 2020 15:21:21 +0200	[thread overview]
Message-ID: <gkrsgdhvyjy.fsf@arm.com> (raw)
In-Reply-To: <20200724115347.GM32057@gate.crashing.org> (Segher Boessenkool's message of "Fri, 24 Jul 2020 06:53:47 -0500")

Segher Boessenkool <segher@kernel.crashing.org> writes:

> Hi!
>
> On Fri, Jul 24, 2020 at 09:01:33AM +0200, Andrea Corallo wrote:
>> Segher Boessenkool <segher@kernel.crashing.org> writes:
>> >> Correct, it's a sliding window only because the real load address is not
>> >> known to the compiler and the algorithm is conservative.  I believe we
>> >> could use ASM_OUTPUT_ALIGN_WITH_NOP if we align each function to (al
>> >> least) the granule size, then we should be able to insert 'nop aligned
>> >> labels' precisely.
>> >
>> > Yeah, we have similar issues on Power...  Our "granule" (fetch group
>> > size, in our terminology) is 32 typically, but we align functions to
>> > just 16.  This is causing some problems, but aligning to bigger
>> > boundaries isn't a very happy alternative either.  WIP...
>> 
>> Interesting, I was expecting other CPUs to have a similar mechanism.
>
> On old cpus (like the 970) there were at most two branch predictions per
> cycle.  Nowadays, all branches are predicted; not sure when this changed,
> it is pretty long ago already.
>
>> > (We don't have this exact same problem, because our non-ancient cores
>> > can just predict *all* branches in the same cycle).
>> >
>> >> My main fear is that given new cores tend to have big granules code size
>> >> would blow.  One advantage of the implemented algorithm is that even if
>> >> slightly conservative it's impacting code size only where an high branch
>> >> density shows up.
>> >
>> > What is "big granules" for you?
>> 
>> N1 is 8 instructions so 32 bytes as well, I guess this may grow further
>> (my speculation).
>
> It has to sooner rather than later, yeah.  Or the mechanism has to change
> more radically.  Interesting times ahead, I guess :-)

Indeed :)

> About your patch itself.  The basic idea seems fine (I didn't look too
> closely), but do you really need a new RTX class for this?  That is not
> very appetising...

Agree, OTOH I'm not sure about the other options on the table and their
impact, the advantage of this is that the impact is relatively
contained.

  Andrea

  reply	other threads:[~2020-07-24 13:21 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-22 10:02 [PATCH 1/2] Add new RTX instruction class FILLER_INSN Andrea Corallo
2020-07-22 10:09 ` [PATCH 2/2] Aarch64: Add branch diluter pass Andrea Corallo
2020-07-22 10:39   ` Andrew Pinski
2020-07-22 13:53     ` Andrea Corallo
2020-07-22 16:43       ` Segher Boessenkool
2020-07-22 19:45         ` Andrea Corallo
2020-07-23 22:47           ` Segher Boessenkool
2020-07-24  7:01             ` Andrea Corallo
2020-07-24 11:53               ` Segher Boessenkool
2020-07-24 13:21                 ` Andrea Corallo [this message]
2020-07-24 22:09   ` Segher Boessenkool
2020-07-28 18:55     ` Andrea Corallo
2020-07-28 22:07       ` Segher Boessenkool
2020-07-22 12:24 ` [PATCH 1/2] Add new RTX instruction class FILLER_INSN Richard Biener
2020-07-22 13:16   ` Richard Earnshaw (lists)
2020-07-22 14:51   ` Andrea Corallo
2020-07-22 18:41 ` Joseph Myers
2020-07-24 21:18 ` Segher Boessenkool
2020-07-26 18:19   ` Eric Botcazou
2020-07-28 19:29   ` Andrea Corallo
2020-08-19  9:13   ` Andrea Corallo
2020-08-19 10:52     ` Richard Sandiford
2020-08-19 17:28     ` Segher Boessenkool
2020-08-19 16:51 ` Segher Boessenkool
2020-08-19 17:47   ` Andrea Corallo

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