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dkim=none (message not signed) header.d=none;gcc.gnu.org; dmarc=none action=none header.from=arm.com; Received: from DB7PR08MB3594.eurprd08.prod.outlook.com (2603:10a6:10:4e::11) by DBBPR08MB4363.eurprd08.prod.outlook.com (2603:10a6:10:ce::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3216.20; Fri, 24 Jul 2020 07:01:36 +0000 Received: from DB7PR08MB3594.eurprd08.prod.outlook.com ([fe80::9f3:461:834d:7ca]) by DB7PR08MB3594.eurprd08.prod.outlook.com ([fe80::9f3:461:834d:7ca%7]) with mapi id 15.20.3195.028; Fri, 24 Jul 2020 07:01:36 +0000 From: Andrea Corallo To: Segher Boessenkool Cc: Andrew Pinski , Richard Earnshaw , nd , GCC Patches Subject: Re: [PATCH 2/2] Aarch64: Add branch diluter pass References: <20200722164322.GA32057@gate.crashing.org> <20200723224715.GK32057@gate.crashing.org> Date: Fri, 24 Jul 2020 09:01:33 +0200 In-Reply-To: <20200723224715.GK32057@gate.crashing.org> (Segher Boessenkool's message of "Thu, 23 Jul 2020 17:47:15 -0500") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.0.50 (gnu/linux) Content-Type: text/plain X-ClientProxiedBy: LO2P265CA0380.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:a3::32) To DB7PR08MB3594.eurprd08.prod.outlook.com (2603:10a6:10:4e::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from e112547 (217.140.99.251) by LO2P265CA0380.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:a3::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3216.23 via Frontend Transport; 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SFS:(4636009)(46966005)(356005)(36756003)(6862004)(16526019)(81166007)(26005)(47076004)(8676002)(6496006)(82310400002)(186003)(4326008)(86362001)(5660300002)(44832011)(70206006)(8936002)(70586007)(336012)(2906002)(956004)(83380400001)(2616005)(6486002)(54906003)(498600001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jul 2020 07:01:43.6103 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 001611d1-fafe-4383-5917-08d82f9f6c4c X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT033.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR0802MB2321 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, MSGID_FROM_MTA_HEADER, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 24 Jul 2020 07:01:48 -0000 Segher Boessenkool writes: > On Wed, Jul 22, 2020 at 09:45:08PM +0200, Andrea Corallo wrote: >> > Should that actually be a sliding window, or should there actually just >> > not be more than N branches per aligned block of machine code? Like, >> > per fetch group. >> > >> > Can you not use ASM_OUTPUT_ALIGN_WITH_NOP (or ASM_OUTPUT_MAX_SKIP_ALIGN >> > even) then? GCC has infrastructure for that, already. >> >> Correct, it's a sliding window only because the real load address is not >> known to the compiler and the algorithm is conservative. I believe we >> could use ASM_OUTPUT_ALIGN_WITH_NOP if we align each function to (al >> least) the granule size, then we should be able to insert 'nop aligned >> labels' precisely. > > Yeah, we have similar issues on Power... Our "granule" (fetch group > size, in our terminology) is 32 typically, but we align functions to > just 16. This is causing some problems, but aligning to bigger > boundaries isn't a very happy alternative either. WIP... Interesting, I was expecting other CPUs to have a similar mechanism. > (We don't have this exact same problem, because our non-ancient cores > can just predict *all* branches in the same cycle). > >> My main fear is that given new cores tend to have big granules code size >> would blow. One advantage of the implemented algorithm is that even if >> slightly conservative it's impacting code size only where an high branch >> density shows up. > > What is "big granules" for you? N1 is 8 instructions so 32 bytes as well, I guess this may grow further (my speculation). Andrea